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barebox
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Merge branch 'for-next/imx'

This commit is contained in:
Sascha Hauer 2015-09-01 09:43:54 +02:00
parent fae6eea0e6 2eb7fb71ae
commit feeb128788
7 changed files with 51 additions and 147 deletions
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31
arch/arm/boards/phytec-phyflex-imx6/board.c
View File

@ -16,6 +16,7 @@
* Foundation.
*
*/
#define pr_fmt(fmt) "phyFLEX-i.MX6: " fmt
#include <malloc.h>
#include <envfs.h>
@ -27,12 +28,16 @@
#include <of.h>
#include <mach/bbu.h>
#include <fec.h>
#include <globalvar.h>
#include <linux/micrel_phy.h>
#include <mach/iomux-mx6.h>
#include <mach/imx6.h>
#define PHYFLEX_MODULE_REV_1 0x1
#define PHYFLEX_MODULE_REV_2 0x2
#define GPIO_2_11_PD_CTL MX6_PAD_CTL_PUS_100K_DOWN | MX6_PAD_CTL_PUE | MX6_PAD_CTL_PKE | \
MX6_PAD_CTL_SPEED_MED | MX6_PAD_CTL_DSE_40ohm | MX6_PAD_CTL_HYS
@ -64,10 +69,24 @@ static void phyflex_err006282_workaround(void)
gpio_direction_input(MX6_PHYFLEX_ERR006282);
}
static unsigned int pfla02_module_revision;
static unsigned int get_module_rev(void)
{
unsigned int val = 0;
val = gpio_get_value(IMX_GPIO_NR(2, 12));
val |= (gpio_get_value(IMX_GPIO_NR(2, 13)) << 1);
val |= (gpio_get_value(IMX_GPIO_NR(2, 14)) << 2);
val |= (gpio_get_value(IMX_GPIO_NR(2, 15)) << 3);
return 16 - val;
}
static int phytec_pfla02_init(void)
{
int ret;
char *environment_path;
char *environment_path, *envdev;
if (!of_machine_is_compatible("phytec,imx6q-pfla02") &&
!of_machine_is_compatible("phytec,imx6dl-pfla02") &&
@ -78,17 +97,25 @@ static int phytec_pfla02_init(void)
imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT);
pfla02_module_revision = get_module_rev();
globalvar_add_simple_int("board.revision", &pfla02_module_revision, "%u");
pr_info("Module Revision: %u\n", pfla02_module_revision);
switch (bootsource_get()) {
case BOOTSOURCE_MMC:
environment_path = asprintf("/chosen/environment-sd%d",
bootsource_get_instance() + 1);
envdev = "MMC";
break;
case BOOTSOURCE_NAND:
environment_path = asprintf("/chosen/environment-nand");
envdev = "NAND flash";
break;
default:
case BOOTSOURCE_SPI:
environment_path = asprintf("/chosen/environment-spinor");
envdev = "SPI NOR flash";
break;
}
@ -99,6 +126,8 @@ static int phytec_pfla02_init(void)
free(environment_path);
pr_notice("Using environment in %s\n", envdev);
return 0;
}
device_initcall(phytec_pfla02_init);

4
arch/arm/dts/imx6dl-phytec-pfla02.dtsi
View File

@ -16,7 +16,3 @@
model = "Phytec phyFLEX-i.MX6 Dual Lite";
compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
};
&ecspi3 {
status = "okay";
};

4
arch/arm/dts/imx6q-phytec-pbab01.dts
View File

@ -16,8 +16,4 @@
/ {
model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
compatible = "phytec,imx6x-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
chosen {
linux,stdout-path = &uart4;
};
};

4
arch/arm/dts/imx6q-phytec-pfla02.dtsi
View File

@ -17,7 +17,3 @@
model = "Phytec phyFLEX-i.MX6 Quad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
};
&ecspi3 {
status = "okay";
};

16
arch/arm/dts/imx6qdl-phytec-pbab01.dtsi
View File

@ -9,22 +9,8 @@
* http://www.gnu.org/copyleft/gpl.html
*/
&fec {
status = "okay";
};
#include <arm/imx6qdl-phytec-pbab01.dtsi>
&uart1 {
status = "okay";
};
&uart4 {
status = "okay";
};
&usdhc2 {
status = "okay";
};
&usdhc3 {
status = "okay";
};

137
arch/arm/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -9,7 +9,14 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include <arm/imx6qdl-phytec-pfla02.dtsi>
/ {
memory {
/* let barebox fill the memory node */
reg = <0 0>;
};
chosen {
environment-nand {
compatible = "barebox,environment";
@ -50,17 +57,7 @@
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "disabled";
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
flash: m25p80@0 {
compatible = "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
@ -87,12 +84,7 @@
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "disabled";
mdio {
#address-cells = <1>;
@ -108,10 +100,6 @@
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
@ -143,44 +131,20 @@
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl-0 = <&pinctrl_hog>, <&pinctrl_rev>;
ecspi3 {
pinctrl_ecspi3: ecspi3grp {
imx6q-phytec-pfla02 {
pinctrl_rev: revgrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x80000000
MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x80000000
MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x80000000
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000
>;
};
};
enet {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand: gpmi-nand {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
@ -204,79 +168,13 @@
>;
};
};
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000
>;
};
};
uart4 {
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
usdhc2 {
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};
};
&ocotp {
barebox,provide-mac-address = <&fec 0x620>;
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
cd-gpios = <&gpio1 27 0>;
wp-gpios = <&gpio1 29 0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
@ -284,6 +182,7 @@
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;

2
arch/arm/mach-imx/Kconfig
View File

@ -179,12 +179,14 @@ config ARCH_IMX6
select ARCH_HAS_FEC_IMX
select CPU_V7
select PINCTRL_IMX_IOMUX_V3
select OFTREE
select COMMON_CLK_OF_PROVIDER
select HW_HAS_PCI
config ARCH_IMX6SX
bool
select ARCH_IMX6
select OFTREE
select COMMON_CLK_OF_PROVIDER
config IMX_MULTI_BOARDS