e1000: Consolidate register offset fixups
Consolidate all code taking care on CSR offset differences for i210 chips into a single place in the driver and integrate that funcionality into e1000_{read,write}_reg functions. This way we can get rid of all those if (hw->mac_type == e1000_igb) { .... } else { .... } snippets sprinkled all across the driver code. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -389,6 +389,11 @@ struct e1000_tx_desc {
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#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
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#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
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#define E1000_MIGHT_BE_REMAPPED 0x80000000 /* Flag indicating that on
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some variants of the chip
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register offset might be
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different */
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/* Register Set. (82543, 82544)
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*
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* Registers are defined to be 32 bits and should be accessed as 32 bit values.
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@ -429,17 +434,17 @@ struct e1000_tx_desc {
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#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
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#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
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#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
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#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
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#define E1000_PHY_CTRL (E1000_MIGHT_BE_REMAPPED | 0x00F10) /* PHY Control Register in CSR */
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#define E1000_I210_PHY_CTRL 0x00E14 /* PHY Control Register in CSR */
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#define FEXTNVM_SW_CONFIG 0x0001
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#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
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#define E1000_PBS 0x01008 /* Packet Buffer Size */
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#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
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#define E1000_EEMNGCTL (E1000_MIGHT_BE_REMAPPED | 0x01010) /* MNG EEprom Control */
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#define E1000_I210_EEMNGCTL 0x12030 /* MNG EEprom Control */
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#define E1000_FLASH_UPDATES 1000
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#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
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#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
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#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
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#define E1000_EEWR (E1000_MIGHT_BE_REMAPPED | 0x0102C) /* EEPROM Write Register - RW */
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#define E1000_I210_EEWR 0x12018 /* EEPROM Write Register - RW */
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#define E1000_FLSWCTL 0x01030 /* FLASH control register */
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#define E1000_FLSWDATA 0x01034 /* FLASH data register */
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@ -451,14 +451,10 @@ static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
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int32_t done = E1000_ERR_EEPROM;
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for (i = 0; i < attempts; i++) {
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if (eerd == E1000_EEPROM_POLL_READ) {
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if (eerd == E1000_EEPROM_POLL_READ)
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reg = e1000_read_reg(hw, E1000_EERD);
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} else {
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if (hw->mac_type == e1000_igb)
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reg = e1000_read_reg(hw, E1000_I210_EEWR);
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else
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reg = e1000_read_reg(hw, E1000_EEWR);
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}
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else
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reg = e1000_read_reg(hw, E1000_EEWR);
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if (reg & E1000_EEPROM_RW_REG_DONE) {
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done = E1000_SUCCESS;
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@ -1184,14 +1184,11 @@ static int32_t e1000_set_d0_lplu_state_off(struct e1000_hw *hw)
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if (hw->mac_type <= e1000_82547_rev_2)
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return E1000_SUCCESS;
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if (hw->mac_type == e1000_ich8lan) {
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if (hw->mac_type == e1000_ich8lan ||
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hw->mac_type == e1000_igb) {
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phy_ctrl = e1000_read_reg(hw, E1000_PHY_CTRL);
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phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
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e1000_write_reg(hw, E1000_PHY_CTRL, phy_ctrl);
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} else if (hw->mac_type == e1000_igb) {
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phy_ctrl = e1000_read_reg(hw, E1000_I210_PHY_CTRL);
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phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
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e1000_write_reg(hw, E1000_I210_PHY_CTRL, phy_ctrl);
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} else {
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ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
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&phy_data);
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@ -2745,13 +2742,9 @@ static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw)
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case e1000_82572:
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case e1000_igb:
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while (timeout) {
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if (hw->mac_type == e1000_igb) {
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if (e1000_read_reg(hw, E1000_I210_EEMNGCTL) & cfg_mask)
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break;
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} else {
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if (e1000_read_reg(hw, E1000_EEMNGCTL) & cfg_mask)
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break;
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}
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if (e1000_read_reg(hw, E1000_EEMNGCTL) & cfg_mask)
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break;
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mdelay(1);
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timeout--;
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}
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@ -2,13 +2,38 @@
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#include "e1000.h"
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static uint32_t e1000_true_offset(struct e1000_hw *hw, uint32_t reg)
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{
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if (reg & E1000_MIGHT_BE_REMAPPED) {
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reg &= ~E1000_MIGHT_BE_REMAPPED;
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if (hw->mac_type == e1000_igb) {
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switch (reg) {
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case E1000_EEWR:
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reg = E1000_I210_EEWR;
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break;
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case E1000_PHY_CTRL:
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reg = E1000_I210_PHY_CTRL;
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break;
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case E1000_EEMNGCTL:
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reg = E1000_I210_EEMNGCTL;
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break;
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}
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};
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}
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return reg;
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}
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void e1000_write_reg(struct e1000_hw *hw, uint32_t reg, uint32_t value)
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{
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reg = e1000_true_offset(hw, reg);
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writel(value, hw->hw_addr + reg);
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}
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uint32_t e1000_read_reg(struct e1000_hw *hw, uint32_t reg)
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{
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reg = e1000_true_offset(hw, reg);
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return readl(hw->hw_addr + reg);
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}
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