/* * Copyright (C) 2007 Sascha Hauer, Pengutronix * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA * */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static struct device_d cfi_dev = { .name = "cfi_flash", .map_base = 0xa0000000, .size = 64 * 1024 * 1024, }; static struct memory_platform_data ram_pdata = { .name = "ram0", .flags = DEVFS_RDWR, }; static struct device_d sdram_dev = { .name = "mem", .map_base = 0x80000000, .size = 128 * 1024 * 1024, .platform_data = &ram_pdata, }; static struct fec_platform_data fec_info = { .xcv_type = MII100, }; static struct device_d fec_dev = { .name = "fec_imx", .map_base = 0x50038000, .platform_data = &fec_info, }; /* * SMSC 9217 network controller */ static struct device_d smc911x_dev = { .name = "smc911x", .map_base = IMX_CS5_BASE, .size = IMX_CS5_RANGE, /* area size */ }; static int f3s_devices_init(void) { register_device(&cfi_dev); register_device(&sdram_dev); register_device(&smc911x_dev); /* FEC is currently broken. It seems to work * shortly but after a few moments the board * goes to nirvana */ // register_device(&fec_dev); /* * Create partitions that should be * not touched by any regular user */ devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */ devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); /* environment */ armlinux_add_dram(&sdram_dev); armlinux_set_bootparams((void *)0x80000100); armlinux_set_architecture(MACH_TYPE_PCM037); /* FIXME */ return 0; } device_initcall(f3s_devices_init); static struct device_d f3s_serial_device = { .name = "imx_serial", .map_base = IMX_UART1_BASE, .size = 4096, }; static struct pad_desc f3s_pads[] = { MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, MX35_PAD_FEC_RX_DV__FEC_RX_DV, MX35_PAD_FEC_COL__FEC_COL, MX35_PAD_FEC_RDATA0__FEC_RDATA_0, MX35_PAD_FEC_TDATA0__FEC_TDATA_0, MX35_PAD_FEC_TX_EN__FEC_TX_EN, MX35_PAD_FEC_MDC__FEC_MDC, MX35_PAD_FEC_MDIO__FEC_MDIO, MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, MX35_PAD_FEC_CRS__FEC_CRS, MX35_PAD_FEC_RDATA0__FEC_RDATA_0, MX35_PAD_FEC_TDATA0__FEC_TDATA_0, MX35_PAD_FEC_RDATA1__FEC_RDATA_1, MX35_PAD_FEC_TDATA1__FEC_TDATA_1, MX35_PAD_FEC_RDATA2__FEC_RDATA_2, MX35_PAD_FEC_TDATA2__FEC_TDATA_2, MX35_PAD_FEC_RDATA3__FEC_RDATA_3, MX35_PAD_FEC_TDATA3__FEC_TDATA_3, MX35_PAD_RXD1__UART1_RXD_MUX, MX35_PAD_TXD1__UART1_TXD_MUX, MX35_PAD_RTS1__UART1_RTS, MX35_PAD_CTS1__UART1_CTS, }; static int f3s_console_init(void) { mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); register_device(&f3s_serial_device); return 0; } console_initcall(f3s_console_init); static int f3s_core_setup(void) { u32 tmp; writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */ writel(0x22252521, CSCR_L(5)); writel(0x22220A00, CSCR_A(5)); /* FIXME: The rest is currently done in Assembler. Remove assembler * config once the board is running stable */ return 0; /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ writel(0x77777777, IMX_AIPS1_BASE); writel(0x77777777, IMX_AIPS1_BASE + 0x4); writel(0x77777777, IMX_AIPS2_BASE); writel(0x77777777, IMX_AIPS2_BASE + 0x4); /* * Clear the on and off peripheral modules Supervisor Protect bit * for SDMA to access them. Did not change the AIPS control registers * (offset 0x20) access type */ writel(0x0, IMX_AIPS1_BASE + 0x40); writel(0x0, IMX_AIPS1_BASE + 0x44); writel(0x0, IMX_AIPS1_BASE + 0x48); writel(0x0, IMX_AIPS1_BASE + 0x4C); tmp = readl(IMX_AIPS1_BASE + 0x50); tmp &= 0x00FFFFFF; writel(tmp, IMX_AIPS1_BASE + 0x50); writel(0x0, IMX_AIPS2_BASE + 0x40); writel(0x0, IMX_AIPS2_BASE + 0x44); writel(0x0, IMX_AIPS2_BASE + 0x48); writel(0x0, IMX_AIPS2_BASE + 0x4C); tmp = readl(IMX_AIPS2_BASE + 0x50); tmp &= 0x00FFFFFF; writel(tmp, IMX_AIPS2_BASE + 0x50); /* MAX (Multi-Layer AHB Crossbar Switch) setup */ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ #define MAX_PARAM1 0x00302154 writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */ writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ /* SGPCR - always park on last master */ writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ /* MGPCR - restore default values */ writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ return 0; } core_initcall(f3s_core_setup);