220 lines
8.0 KiB
C
220 lines
8.0 KiB
C
/*
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* ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
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* Based on Linux driver:
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* Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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* Ported to Barebox:
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* Copyright (C) 2013 Oleksij Rempel <linux@rempel-privat.de>
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*
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* Thanks to Atheros for providing hardware and documentation
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* enabling me to write this driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _AR2313_2_H_
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#define _AR2313_2_H_
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#include <net.h>
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#include <mach/ar231x_platform.h>
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/* Allocate 64 RX buffers. This will reduce packet loss, until we will start
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* processing them. It is important in noisy network with lots of broadcasts. */
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#define AR2313_RXDSC_ENTRIES 64
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#define DSC_NEXT(idx) (((idx) + 1) & (AR2313_RXDSC_ENTRIES - 1))
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/* Use system default buffers size. At the moment of writing it was 1518 */
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#define AR2313_RX_BUFSIZE PKTSIZE
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#define CRC_LEN 4
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/**
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* DMA controller
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*/
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#define AR231X_DMA_BUS_MODE 0x00 /* (CSR0) */
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#define AR231X_DMA_TX_POLL 0x04 /* (CSR1) */
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#define AR231X_DMA_RX_POLL 0x08 /* (CSR2) */
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#define AR231X_DMA_RX_RING 0x0c /* (CSR3) */
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#define AR231X_DMA_TX_RING 0x10 /* (CSR4) */
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#define AR231X_DMA_STATUS 0x14 /* (CSR5) */
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#define AR231X_DMA_CONTROL 0x18 /* (CSR6) */
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#define AR231X_DMA_INTR_ENA 0x1c /* (CSR7) */
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#define AR231X_DMA_RX_MISSED 0x20 /* (CSR8) */
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/* reserverd 0x24-0x4c (CSR9-19) */
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#define AR231X_DMA_CUR_TX_BUF_ADDR 0x50 /* (CSR20) */
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#define AR231X_DMA_CUR_RX_BUF_ADDR 0x54 /* (CSR21) */
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/**
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* Ethernet controller
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*/
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#define AR231X_ETH_MAC_CONTROL 0x00
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#define AR231X_ETH_MAC_ADDR1 0x04
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#define AR231X_ETH_MAC_ADDR2 0x08
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#define AR231X_ETH_MCAST_TABLE1 0x0c
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#define AR231X_ETH_MCAST_TABLE2 0x10
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#define AR231X_ETH_MII_ADDR 0x14
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#define AR231X_ETH_MII_DATA 0x18
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#define AR231X_ETH_FLOW_CONTROL 0x1c
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#define AR231X_ETH_VLAN_TAG 0x20
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/* pad 0x24 - 0x3c */
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/* ucast_table 0x40-0x5c */
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/**
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* RX descriptor status bits. ar231x_descr.status
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*/
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#define DMA_RX_ERR_CRC BIT(1)
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#define DMA_RX_ERR_DRIB BIT(2)
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#define DMA_RX_ERR_MII BIT(3)
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#define DMA_RX_EV2 BIT(5)
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#define DMA_RX_ERR_COL BIT(6)
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#define DMA_RX_LONG BIT(7)
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#define DMA_RX_LS BIT(8) /* last descriptor */
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#define DMA_RX_FS BIT(9) /* first descriptor */
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#define DMA_RX_MF BIT(10) /* multicast frame */
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#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
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#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
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#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
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#define DMA_RX_ERROR BIT(15) /* error summary */
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#define DMA_RX_LEN_MASK 0x3fff0000
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#define DMA_RX_LEN_SHIFT 16
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#define DMA_RX_FILT BIT(30)
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#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
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#define DMA_RX_FSLS (DMA_RX_LS | DMA_RX_FS)
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#define DMA_RX_MASK (DMA_RX_FSLS | DMA_RX_MF | DMA_RX_ERROR)
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/**
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* RX descriptor configuration bits. ar231x_descr.devcs
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*/
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#define DMA_RX1_BSIZE_MASK 0x000007ff
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#define DMA_RX1_BSIZE_SHIFT 0
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#define DMA_RX1_CHAINED BIT(24)
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#define DMA_RX1_RER BIT(25)
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/**
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* TX descriptor status fields. ar231x_descr.status
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*/
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#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
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#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
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#define DMA_TX_COL_MASK 0x78
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#define DMA_TX_COL_SHIFT 3
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#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
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#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
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#define DMA_TX_ERR_LATE BIT(9) /* late collision */
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#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
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#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
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#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
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#define DMA_TX_ERROR BIT(15) /* frame aborted */
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#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
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/**
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* TX descriptor configuration bits. ar231x_descr.devcs
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*/
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#define DMA_TX1_BSIZE_MASK 0x000007ff
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#define DMA_TX1_BSIZE_SHIFT 0
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#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
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#define DMA_TX1_TER BIT(25) /* transmit end of ring */
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#define DMA_TX1_FS BIT(29) /* first segment */
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#define DMA_TX1_LS BIT(30) /* last segment */
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#define DMA_TX1_IC BIT(31) /* interrupt on completion */
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#define DMA_TX1_DEFAULT (DMA_TX1_FS | DMA_TX1_LS | DMA_TX1_TER)
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#define MAC_CONTROL_RE BIT(2) /* receive enable */
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#define MAC_CONTROL_TE BIT(3) /* transmit enable */
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#define MAC_CONTROL_DC BIT(5) /* Deferral check */
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#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
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#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
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#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
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#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
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#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
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#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
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#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
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#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
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#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
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#define MAC_CONTROL_PR BIT(18) /* promiscuous mode
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* (valid frames only) */
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#define MAC_CONTROL_PM BIT(19) /* pass multicast */
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#define MAC_CONTROL_F BIT(20) /* full-duplex */
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#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
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#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
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#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
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#define MAC_CONTROL_RA BIT(31) /* receive all
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* (valid and invalid frames) */
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#define MII_ADDR_BUSY BIT(0)
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#define MII_ADDR_WRITE BIT(1)
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#define MII_ADDR_REG_SHIFT 6
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#define MII_ADDR_PHY_SHIFT 11
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#define MII_DATA_SHIFT 0
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#define FLOW_CONTROL_FCE BIT(1)
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#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
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#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
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#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
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#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
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#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
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#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
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#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
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#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
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#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
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#define DMA_STATUS_RI BIT(6) /* receive interrupt */
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#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
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#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
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#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
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#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
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#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
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#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
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#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
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#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
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#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
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#define DMA_STATUS_EB_SHIFT 23 /* error bits */
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#define DMA_CONTROL_SR BIT(1) /* start receive */
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#define DMA_CONTROL_ST BIT(13) /* start transmit */
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#define DMA_CONTROL_SF BIT(21) /* store and forward */
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struct ar231x_descr {
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u32 status; /* OWN, Device control and status. */
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u32 devcs; /* Packet control bitmap + Length. */
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u32 buffer_ptr; /* Pointer to packet buffer. */
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u32 next_dsc_ptr; /* Pointer to next descriptor in chain. */
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};
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/**
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* Struct private for the Sibyte.
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*
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* Elements are grouped so variables used by the tx handling goes
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* together, and will go into the same cache lines etc. in order to
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* avoid cache line contention between the rx and tx handling on SMP.
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*
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* Frequently accessed variables are put at the beginning of the
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* struct to help the compiler generate better/shorter code.
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*/
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struct ar231x_eth_priv {
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struct ar231x_eth_platform_data *cfg;
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u8 *mac;
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void __iomem *phy_regs;
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void __iomem *eth_regs;
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void __iomem *dma_regs;
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void __iomem *reset_regs;
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struct eth_device edev;
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struct mii_bus miibus;
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struct ar231x_descr *tx_ring;
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struct ar231x_descr *rx_ring;
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struct ar231x_descr *next_rxdsc;
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u8 kill_rx_ring;
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void *rx_buffer;
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int oldduplex;
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void (*reset_bit)(u32 val, enum reset_state state);
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};
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#endif /* _AR2313_H_ */
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