148 lines
3.6 KiB
C
148 lines
3.6 KiB
C
/*
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* linux/arch/arm/mach-nomadik/timer.c
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*
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* Copyright (C) 2008 STMicroelectronics
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* Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <clock.h>
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#include <io.h>
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#include <init.h>
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#include <driver.h>
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#include <errno.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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/*
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* The MTU device hosts four different counters, with 4 set of
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* registers. These are register names.
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*/
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#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
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#define MTU_RIS 0x04 /* Raw interrupt status */
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#define MTU_MIS 0x08 /* Masked interrupt status */
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#define MTU_ICR 0x0C /* Interrupt clear register */
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/* per-timer registers take 0..3 as argument */
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#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
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#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
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#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
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#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
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/* bits for the control register */
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#define MTU_CRn_ENA 0x80
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#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
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#define MTU_CRn_PRESCALE_MASK 0x0c
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#define MTU_CRn_PRESCALE_1 0x00
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#define MTU_CRn_PRESCALE_16 0x04
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#define MTU_CRn_PRESCALE_256 0x08
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#define MTU_CRn_32BITS 0x02
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#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
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/* Other registers are usual amba/primecell registers, currently not used */
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#define MTU_ITCR 0xff0
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#define MTU_ITOP 0xff4
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#define MTU_PERIPH_ID0 0xfe0
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#define MTU_PERIPH_ID1 0xfe4
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#define MTU_PERIPH_ID2 0xfe8
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#define MTU_PERIPH_ID3 0xfeC
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#define MTU_PCELL0 0xff0
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#define MTU_PCELL1 0xff4
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#define MTU_PCELL2 0xff8
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#define MTU_PCELL3 0xffC
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static __iomem void *mtu_base;
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static u32 clk_prescale;
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static u32 nmdk_cycle; /* write-once */
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/*
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* clocksource: the MTU device is a decrementing counters, so we negate
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* the value being read.
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*/
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static uint64_t nmdk_read_timer(void)
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{
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return nmdk_cycle - readl(mtu_base + MTU_VAL(0));
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}
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static struct clocksource nmdk_clksrc = {
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.read = nmdk_read_timer,
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.shift = 20,
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.mask = CLOCKSOURCE_MASK(32),
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};
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static void nmdk_timer_reset(void)
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{
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u32 cr;
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/* Disable */
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writel(0, mtu_base + MTU_CR(0)); /* off */
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/* configure load and background-load, and fire it up */
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writel(nmdk_cycle, mtu_base + MTU_LR(0));
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writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
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cr = clk_prescale | MTU_CRn_32BITS;
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writel(cr, mtu_base + MTU_CR(0));
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writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
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}
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static int nmdk_mtu_probe(struct device_d *dev)
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{
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static struct clk *mtu_clk;
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u32 rate;
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int ret;
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mtu_clk = clk_get(dev, NULL);
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if (IS_ERR(mtu_clk)) {
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ret = PTR_ERR(mtu_clk);
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dev_err(dev, "clock not found: %d\n", ret);
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return ret;
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}
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ret = clk_enable(mtu_clk);
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if (ret < 0) {
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dev_err(dev, "clock failed to enable: %d\n", ret);
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clk_put(mtu_clk);
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return ret;
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}
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rate = clk_get_rate(mtu_clk);
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if (rate > 32000000) {
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rate /= 16;
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clk_prescale = MTU_CRn_PRESCALE_16;
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} else {
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clk_prescale = MTU_CRn_PRESCALE_1;
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}
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nmdk_cycle = (rate + 1000 / 2) / 1000;
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/* Save global pointer to mtu, used by functions above */
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mtu_base = dev_request_mem_region(dev, 0);
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/* Init the timer and register clocksource */
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nmdk_timer_reset();
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nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
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init_clock(&nmdk_clksrc);
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return 0;
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}
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static struct driver_d nmdk_mtu_driver = {
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.name = "nomadik_mtu",
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.probe = nmdk_mtu_probe,
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};
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static int nmdk_mtu_init(void)
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{
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return platform_driver_register(&nmdk_mtu_driver);
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}
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coredevice_initcall(nmdk_mtu_init);
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