591 lines
15 KiB
C
591 lines
15 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc
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* Copyright (C) 2002 Motorola GSG-China
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* 2009 Marc Kleine-Budde, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Author:
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* Darius Augulis, Teltonika Inc.
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*
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* Desc.:
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* Implementation of I2C Adapter/Algorithm Driver
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* for I2C Bus integrated in Freescale i.MX/MXC processors and
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* 85xx processors.
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*
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* Derived from Motorola GSG China I2C example driver
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*
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* Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
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* Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
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* Copyright (C) 2007 RightHand Technologies, Inc.
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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*/
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#include <clock.h>
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <of.h>
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#include <malloc.h>
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#include <types.h>
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#include <xfuncs.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <io.h>
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#include <i2c/i2c.h>
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#include <mach/clock.h>
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/* This will be the driver name */
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#define DRIVER_NAME "i2c-fsl"
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/* Default value */
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#define FSL_I2C_BIT_RATE 100000 /* 100kHz */
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/* FSL I2C registers */
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#define FSL_I2C_IADR 0x00 /* i2c slave address */
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#define FSL_I2C_IFDR 0x04 /* i2c frequency divider */
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#define FSL_I2C_I2CR 0x08 /* i2c control */
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#define FSL_I2C_I2SR 0x0C /* i2c status */
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#define FSL_I2C_I2DR 0x10 /* i2c transfer data */
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#define FSL_I2C_DFSRR 0x14 /* i2c digital filter sampling rate */
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/* Bits of FSL I2C registers */
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#define I2SR_RXAK 0x01
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#define I2SR_IIF 0x02
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#define I2SR_SRW 0x04
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#define I2SR_IAL 0x10
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#define I2SR_IBB 0x20
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#define I2SR_IAAS 0x40
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#define I2SR_ICF 0x80
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#define I2CR_RSTA 0x04
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#define I2CR_TXAK 0x08
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#define I2CR_MTX 0x10
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#define I2CR_MSTA 0x20
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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/*
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* sorted list of clock divider, register value pairs
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* taken from table 26-5, p.26-9, Freescale i.MX
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* Integrated Portable System Processor Reference Manual
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* Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
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*
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* Duplicated divider values removed from list
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*/
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#ifndef CONFIG_PPC
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static u16 i2c_clk_div[50][2] = {
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{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
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{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
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{ 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
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{ 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
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{ 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
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{ 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
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{ 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
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{ 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
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{ 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
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{ 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
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{ 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
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{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
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{ 3072, 0x1E }, { 3840, 0x1F }
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};
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#endif
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struct fsl_i2c_struct {
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void __iomem *base;
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struct clk *clk;
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struct i2c_adapter adapter;
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unsigned int disable_delay;
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int stopped;
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unsigned int ifdr; /* FSL_I2C_IFDR */
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unsigned int dfsrr; /* FSL_I2C_DFSRR */
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};
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#define to_fsl_i2c_struct(a) container_of(a, struct fsl_i2c_struct, adapter)
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#ifdef CONFIG_I2C_DEBUG
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static void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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u32 reg_cr, reg_sr;
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reg_cr = readb(i2c_fsl->base + FSL_I2C_I2CR);
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reg_sr = readb(i2c_fsl->base + FSL_I2C_I2SR);
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dev_dbg(adapter->dev, "CONTROL:\t"
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"IEN =%d, IIEN=%d, MSTA=%d, MTX =%d, TXAK=%d, RSTA=%d\n",
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(reg_cr & I2CR_IEN ? 1 : 0), (reg_cr & I2CR_IIEN ? 1 : 0),
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(reg_cr & I2CR_MSTA ? 1 : 0), (reg_cr & I2CR_MTX ? 1 : 0),
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(reg_cr & I2CR_TXAK ? 1 : 0), (reg_cr & I2CR_RSTA ? 1 : 0));
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dev_dbg(adapter->dev, "STATUS:\t"
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"ICF =%d, IAAS=%d, IB =%d, IAL =%d, SRW =%d, IIF =%d, RXAK=%d\n",
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(reg_sr & I2SR_ICF ? 1 : 0), (reg_sr & I2SR_IAAS ? 1 : 0),
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(reg_sr & I2SR_IBB ? 1 : 0), (reg_sr & I2SR_IAL ? 1 : 0),
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(reg_sr & I2SR_SRW ? 1 : 0), (reg_sr & I2SR_IIF ? 1 : 0),
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(reg_sr & I2SR_RXAK ? 1 : 0));
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}
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#else
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static inline void i2c_fsl_dump_reg(struct i2c_adapter *adapter)
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{
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return;
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}
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#endif
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static int i2c_fsl_bus_busy(struct i2c_adapter *adapter, int for_busy)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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uint64_t start;
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unsigned int temp;
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start = get_time_ns();
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while (1) {
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temp = readb(base + FSL_I2C_I2SR);
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if (for_busy && (temp & I2SR_IBB))
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break;
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if (!for_busy && !(temp & I2SR_IBB))
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break;
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if (is_timeout(start, 500 * MSECOND)) {
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dev_err(&adapter->dev,
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"<%s> timeout waiting for I2C bus %s\n",
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__func__,for_busy ? "busy" : "not busy");
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return -EIO;
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}
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}
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return 0;
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}
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static int i2c_fsl_trx_complete(struct i2c_adapter *adapter)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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uint64_t start;
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start = get_time_ns();
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while (1) {
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unsigned int reg = readb(base + FSL_I2C_I2SR);
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if (reg & I2SR_IIF)
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break;
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if (is_timeout(start, 100 * MSECOND)) {
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dev_err(&adapter->dev, "<%s> TXR timeout\n", __func__);
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return -EIO;
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}
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}
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writeb(0, base + FSL_I2C_I2SR);
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return 0;
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}
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static int i2c_fsl_acked(struct i2c_adapter *adapter)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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uint64_t start;
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start = get_time_ns();
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while (1) {
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unsigned int reg = readb(base + FSL_I2C_I2SR);
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if (!(reg & I2SR_RXAK))
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break;
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if (is_timeout(start, MSECOND)) {
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dev_dbg(&adapter->dev, "<%s> No ACK\n", __func__);
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return -EIO;
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}
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}
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return 0;
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}
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static int i2c_fsl_start(struct i2c_adapter *adapter)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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unsigned int temp = 0;
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int result;
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writeb(i2c_fsl->ifdr, base + FSL_I2C_IFDR);
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if (i2c_fsl->dfsrr != -1)
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writeb(i2c_fsl->dfsrr, base + FSL_I2C_DFSRR);
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/* Enable I2C controller */
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writeb(0, base + FSL_I2C_I2SR);
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writeb(I2CR_IEN, base + FSL_I2C_I2CR);
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/* Wait controller to be stable */
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udelay(100);
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/* Start I2C transaction */
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temp = readb(base + FSL_I2C_I2CR);
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temp |= I2CR_MSTA;
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writeb(temp, base + FSL_I2C_I2CR);
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result = i2c_fsl_bus_busy(adapter, 1);
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if (result)
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return result;
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i2c_fsl->stopped = 0;
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temp |= I2CR_MTX | I2CR_TXAK;
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writeb(temp, base + FSL_I2C_I2CR);
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return result;
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}
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static void i2c_fsl_stop(struct i2c_adapter *adapter)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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unsigned int temp = 0;
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if (!i2c_fsl->stopped) {
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/* Stop I2C transaction */
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temp = readb(base + FSL_I2C_I2CR);
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temp &= ~(I2CR_MSTA | I2CR_MTX);
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writeb(temp, base + FSL_I2C_I2CR);
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/* wait for the stop condition to be send, otherwise the i2c
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* controller is disabled before the STOP is sent completely */
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i2c_fsl->stopped = i2c_fsl_bus_busy(adapter, 0) ? 0 : 1;
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}
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if (!i2c_fsl->stopped) {
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i2c_fsl_bus_busy(adapter, 0);
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i2c_fsl->stopped = 1;
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}
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/* Disable I2C controller, and force our state to stopped */
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writeb(0, base + FSL_I2C_I2CR);
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}
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#ifdef CONFIG_PPC
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static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
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unsigned int rate)
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{
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void __iomem *base;
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unsigned int i2c_clk;
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unsigned short divider;
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed. That means that we
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* want the first divider that is equal to or greater than the
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* calculated divider.
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*/
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u8 dfsr, fdr;
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/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
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unsigned short a, b, ga, gb;
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unsigned long c_div, est_div;
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fdr = 0x31; /* Default if no FDR found */
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base = i2c_fsl->base;
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i2c_clk = fsl_get_i2c_freq();
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divider = min((unsigned short)(i2c_clk / rate), (unsigned short) -1);
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/*
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* Condition 1: dfsr <= 50ns/T (T=period of I2C source clock in ns).
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* or (dfsr * T) <= 50ns.
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* Translate to dfsr = 5 * Frequency / 100,000,000
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*/
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dfsr = (5 * (i2c_clk / 1000)) / 100000;
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dev_dbg(&i2c_fsl->adapter.dev,
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"<%s> requested speed:%d, i2c_clk:%d\n", __func__,
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rate, i2c_clk);
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if (!dfsr)
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dfsr = 1;
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est_div = ~0;
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for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
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for (gb = 0; gb < 8; gb++) {
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b = 16 << gb;
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c_div = b * (a + ((3*dfsr)/b)*2);
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if ((c_div > divider) && (c_div < est_div)) {
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unsigned short bin_gb, bin_ga;
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est_div = c_div;
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bin_gb = gb << 2;
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bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
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fdr = bin_gb | bin_ga;
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rate = i2c_clk / est_div;
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dev_dbg(&i2c_fsl->adapter.dev,
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"FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x,"
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" a:%d, b:%d, speed:%d\n", fdr, est_div,
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ga, gb, a, b, rate);
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/* Condition 2 not accounted for */
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dev_dbg(&i2c_fsl->adapter.dev,
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"Tr <= %d ns\n", (b - 3 * dfsr) *
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1000000 / (i2c_clk / 1000));
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}
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}
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if (a == 20)
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a += 2;
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if (a == 24)
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a += 4;
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}
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dev_dbg(&i2c_fsl->adapter.dev,
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"divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
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dev_dbg(&i2c_fsl->adapter.dev, "FDR:0x%.2x, speed:%d\n", fdr, rate);
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i2c_fsl->ifdr = fdr;
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i2c_fsl->dfsrr = dfsr;
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}
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#else
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static void i2c_fsl_set_clk(struct fsl_i2c_struct *i2c_fsl,
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unsigned int rate)
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{
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unsigned int i2c_clk_rate;
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unsigned int div;
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int i;
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/* Divider value calculation */
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i2c_clk_rate = clk_get_rate(i2c_fsl->clk);
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div = (i2c_clk_rate + rate - 1) / rate;
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if (div < i2c_clk_div[0][0])
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i = 0;
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else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
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i = ARRAY_SIZE(i2c_clk_div) - 1;
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else
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for (i = 0; i2c_clk_div[i][0] < div; i++)
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;
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/* Store divider value */
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i2c_fsl->ifdr = i2c_clk_div[i][1];
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/*
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* There dummy delay is calculated.
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* It should be about one I2C clock period long.
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* This delay is used in I2C bus disable function
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* to fix chip hardware bug.
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*/
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i2c_fsl->disable_delay =
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(500000U * i2c_clk_div[i][0] + (i2c_clk_rate / 2) - 1) /
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(i2c_clk_rate / 2);
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dev_dbg(&i2c_fsl->adapter.dev, "<%s> I2C_CLK=%d, REQ DIV=%d\n",
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__func__, i2c_clk_rate, div);
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dev_dbg(&i2c_fsl->adapter.dev, "<%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
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__func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
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}
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#endif
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static int i2c_fsl_write(struct i2c_adapter *adapter, struct i2c_msg *msgs)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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int i, result;
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if ( !(msgs->flags & I2C_M_DATA_ONLY) ) {
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dev_dbg(&adapter->dev,
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"<%s> write slave address: addr=0x%02x\n",
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__func__, msgs->addr << 1);
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/* write slave address */
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writeb(msgs->addr << 1, base + FSL_I2C_I2DR);
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result = i2c_fsl_trx_complete(adapter);
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if (result)
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return result;
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result = i2c_fsl_acked(adapter);
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if (result)
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return result;
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}
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/* write data */
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for (i = 0; i < msgs->len; i++) {
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dev_dbg(&adapter->dev,
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"<%s> write byte: B%d=0x%02X\n",
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__func__, i, msgs->buf[i]);
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writeb(msgs->buf[i], base + FSL_I2C_I2DR);
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result = i2c_fsl_trx_complete(adapter);
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if (result)
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return result;
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result = i2c_fsl_acked(adapter);
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if (result)
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return result;
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}
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return 0;
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}
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static int i2c_fsl_read(struct i2c_adapter *adapter, struct i2c_msg *msgs)
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{
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struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
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void __iomem *base = i2c_fsl->base;
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int i, result;
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unsigned int temp;
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/* clear IIF */
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writeb(0x0, base + FSL_I2C_I2SR);
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if ( !(msgs->flags & I2C_M_DATA_ONLY) ) {
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dev_dbg(&adapter->dev,
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"<%s> write slave address: addr=0x%02x\n",
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__func__, (msgs->addr << 1) | 0x01);
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/* write slave address */
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writeb((msgs->addr << 1) | 0x01, base + FSL_I2C_I2DR);
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result = i2c_fsl_trx_complete(adapter);
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if (result)
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return result;
|
|
result = i2c_fsl_acked(adapter);
|
|
if (result)
|
|
return result;
|
|
}
|
|
|
|
/* setup bus to read data */
|
|
temp = readb(base + FSL_I2C_I2CR);
|
|
temp &= ~I2CR_MTX;
|
|
if (msgs->len - 1)
|
|
temp &= ~I2CR_TXAK;
|
|
writeb(temp, base + FSL_I2C_I2CR);
|
|
|
|
readb(base + FSL_I2C_I2DR); /* dummy read */
|
|
|
|
/* read data */
|
|
for (i = 0; i < msgs->len; i++) {
|
|
result = i2c_fsl_trx_complete(adapter);
|
|
if (result)
|
|
return result;
|
|
|
|
if (i == (msgs->len - 1)) {
|
|
/*
|
|
* It must generate STOP before read I2DR to prevent
|
|
* controller from generating another clock cycle
|
|
*/
|
|
temp = readb(base + FSL_I2C_I2CR);
|
|
temp &= ~(I2CR_MSTA | I2CR_MTX);
|
|
writeb(temp, base + FSL_I2C_I2CR);
|
|
|
|
/*
|
|
* adding this delay helps on low bitrates
|
|
*/
|
|
udelay(i2c_fsl->disable_delay);
|
|
|
|
i2c_fsl_bus_busy(adapter, 0);
|
|
i2c_fsl->stopped = 1;
|
|
} else if (i == (msgs->len - 2)) {
|
|
temp = readb(base + FSL_I2C_I2CR);
|
|
temp |= I2CR_TXAK;
|
|
writeb(temp, base + FSL_I2C_I2CR);
|
|
}
|
|
msgs->buf[i] = readb(base + FSL_I2C_I2DR);
|
|
|
|
dev_dbg(&adapter->dev, "<%s> read byte: B%d=0x%02X\n",
|
|
__func__, i, msgs->buf[i]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_fsl_xfer(struct i2c_adapter *adapter,
|
|
struct i2c_msg *msgs, int num)
|
|
{
|
|
struct fsl_i2c_struct *i2c_fsl = to_fsl_i2c_struct(adapter);
|
|
void __iomem *base = i2c_fsl->base;
|
|
unsigned int i, temp;
|
|
int result;
|
|
|
|
/* Start I2C transfer */
|
|
result = i2c_fsl_start(adapter);
|
|
if (result)
|
|
goto fail0;
|
|
|
|
/* read/write data */
|
|
for (i = 0; i < num; i++) {
|
|
if (i && !(msgs[i].flags & I2C_M_DATA_ONLY)) {
|
|
temp = readb(base + FSL_I2C_I2CR);
|
|
temp |= I2CR_RSTA;
|
|
writeb(temp, base + FSL_I2C_I2CR);
|
|
|
|
result = i2c_fsl_bus_busy(adapter, 1);
|
|
if (result)
|
|
goto fail0;
|
|
}
|
|
i2c_fsl_dump_reg(adapter);
|
|
|
|
/* write/read data */
|
|
if (msgs[i].flags & I2C_M_RD)
|
|
result = i2c_fsl_read(adapter, &msgs[i]);
|
|
else
|
|
result = i2c_fsl_write(adapter, &msgs[i]);
|
|
if (result)
|
|
goto fail0;
|
|
}
|
|
|
|
fail0:
|
|
/* Stop I2C transfer */
|
|
i2c_fsl_stop(adapter);
|
|
|
|
return (result < 0) ? result : num;
|
|
}
|
|
|
|
static int __init i2c_fsl_probe(struct device_d *pdev)
|
|
{
|
|
struct fsl_i2c_struct *i2c_fsl;
|
|
struct i2c_platform_data *pdata;
|
|
int ret;
|
|
|
|
pdata = pdev->platform_data;
|
|
|
|
i2c_fsl = kzalloc(sizeof(struct fsl_i2c_struct), GFP_KERNEL);
|
|
|
|
#ifdef CONFIG_COMMON_CLK
|
|
i2c_fsl->clk = clk_get(pdev, NULL);
|
|
if (IS_ERR(i2c_fsl->clk))
|
|
return PTR_ERR(i2c_fsl->clk);
|
|
#endif
|
|
/* Setup i2c_fsl driver structure */
|
|
i2c_fsl->adapter.master_xfer = i2c_fsl_xfer;
|
|
i2c_fsl->adapter.nr = pdev->id;
|
|
i2c_fsl->adapter.dev.parent = pdev;
|
|
i2c_fsl->adapter.dev.device_node = pdev->device_node;
|
|
i2c_fsl->base = dev_request_mem_region(pdev, 0);
|
|
i2c_fsl->dfsrr = -1;
|
|
|
|
/* Set up clock divider */
|
|
if (pdata && pdata->bitrate)
|
|
i2c_fsl_set_clk(i2c_fsl, pdata->bitrate);
|
|
else
|
|
i2c_fsl_set_clk(i2c_fsl, FSL_I2C_BIT_RATE);
|
|
|
|
/* Set up chip registers to defaults */
|
|
writeb(0, i2c_fsl->base + FSL_I2C_I2CR);
|
|
writeb(0, i2c_fsl->base + FSL_I2C_I2SR);
|
|
|
|
/* Add I2C adapter */
|
|
ret = i2c_add_numbered_adapter(&i2c_fsl->adapter);
|
|
if (ret < 0) {
|
|
dev_err(pdev, "registration failed\n");
|
|
goto fail;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail:
|
|
kfree(i2c_fsl);
|
|
return ret;
|
|
}
|
|
|
|
static __maybe_unused struct of_device_id imx_i2c_dt_ids[] = {
|
|
{
|
|
.compatible = "fsl,imx21-i2c",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct driver_d i2c_fsl_driver = {
|
|
.probe = i2c_fsl_probe,
|
|
.name = DRIVER_NAME,
|
|
.of_compatible = DRV_OF_COMPAT(imx_i2c_dt_ids),
|
|
};
|
|
coredevice_platform_driver(i2c_fsl_driver);
|