290 lines
8.7 KiB
C
290 lines
8.7 KiB
C
/*
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* gianfar.h
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*
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* Driver for the Motorola Triple Speed Ethernet Controller
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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* Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc.
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* (C) Copyright 2003, Motorola, Inc.
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* based on tsec.h by Xianghua Xiao and Andy Fleming 2003-2009
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*/
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#ifndef __GIANFAR_H
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#define __GIANFAR_H
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#include <net.h>
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#include <config.h>
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#include <mach/gianfar.h>
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#define MAC_ADDR_LEN 6
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/* TBI register addresses */
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#define GFAR_TBI_CR 0x00
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#define GFAR_TBI_SR 0x01
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#define GFAR_TBI_ANA 0x04
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#define GFAR_TBI_ANLPBPA 0x05
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#define GFAR_TBI_ANEX 0x06
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#define GFAR_TBI_TBICON 0x11
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/* TBI MDIO register bit fields*/
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#define GFAR_TBICON_CLK_SELECT 0x0020
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#define GFAR_TBIANA_ASYMMETRIC_PAUSE 0x0100
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#define GFAR_TBIANA_SYMMETRIC_PAUSE 0x0080
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#define GFAR_TBIANA_HALF_DUPLEX 0x0040
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#define GFAR_TBIANA_FULL_DUPLEX 0x0020
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/* The two reserved bits below are used in AN3869 to enable SGMII. */
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#define GFAR_TBIANA_RESERVED1 0x4000
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#define GFAR_TBIANA_RESERVED15 0x0001
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#define GFAR_TBICR_PHY_RESET 0x8000
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#define GFAR_TBICR_ANEG_ENABLE 0x1000
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#define GFAR_TBICR_RESTART_ANEG 0x0200
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#define GFAR_TBICR_FULL_DUPLEX 0x0100
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#define GFAR_TBICR_SPEED1_SET 0x0040
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/* MAC register bits */
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#define GFAR_MACCFG1_SOFT_RESET 0x80000000
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#define GFAR_MACCFG1_RESET_RX_MC 0x00080000
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#define GFAR_MACCFG1_RESET_TX_MC 0x00040000
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#define GFAR_MACCFG1_RESET_RX_FUN 0x00020000
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#define TESC_MACCFG1_RESET_TX_FUN 0x00010000
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#define GFAR_MACCFG1_LOOPBACK 0x00000100
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#define GFAR_MACCFG1_RX_FLOW 0x00000020
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#define GFAR_MACCFG1_TX_FLOW 0x00000010
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#define GFAR_MACCFG1_SYNCD_RX_EN 0x00000008
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#define GFAR_MACCFG1_RX_EN 0x00000004
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#define GFAR_MACCFG1_SYNCD_TX_EN 0x00000002
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#define GFAR_MACCFG1_TX_EN 0x00000001
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#define MACCFG2_INIT_SETTINGS 0x00007205
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#define GFAR_MACCFG2_FULL_DUPLEX 0x00000001
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#define GFAR_MACCFG2_IF 0x00000300
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#define GFAR_MACCFG2_GMII 0x00000200
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#define GFAR_MACCFG2_MII 0x00000100
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#define ECNTRL_INIT_SETTINGS 0x00001000
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#define GFAR_ECNTRL_TBI_MODE 0x00000020
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#define GFAR_ECNTRL_R100 0x00000008
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#define GFAR_ECNTRL_SGMII_MODE 0x00000002
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#ifndef GFAR_TBIPA_VALUE
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#define GFAR_TBIPA_VALUE 0x1f
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#endif
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#define GFAR_MIIMCFG_INIT_VALUE 0x00000003
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#define GFAR_MIIMCFG_RESET 0x80000000
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#define GFAR_MIIMIND_BUSY 0x00000001
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#define GFAR_MIIMIND_NOTVALID 0x00000004
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#define GFAR_MIIM_CONTROL 0x00000000
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#define GFAR_MIIM_CONTROL_RESET 0x00009140
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#define GFAR_MIIM_CONTROL_INIT 0x00001140
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#define GFAR_MIIM_CONTROL_RESTART 0x00001340
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#define GFAR_MIIM_ANEN 0x00001000
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#define GFAR_MIIM_CR 0x00000000
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#define GFAR_MIIM_CR_RST 0x00008000
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#define GFAR_MIIM_CR_INIT 0x00001000
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#define GFAR_MIIM_STATUS 0x1
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#define GFAR_MIIM_STATUS_AN_DONE 0x00000020
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#define GFAR_MIIM_STATUS_LINK 0x0004
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#define GFAR_MIIM_PHYIR1 0x2
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#define GFAR_MIIM_PHYIR2 0x3
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#define GFAR_MIIM_ANAR 0x4
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#define GFAR_MIIM_ANAR_INIT 0x1e1
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#define GFAR_MIIM_TBI_ANLPBPA 0x5
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#define GFAR_MIIM_TBI_ANLPBPA_HALF 0x00000040
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#define GFAR_MIIM_TBI_ANLPBPA_FULL 0x00000020
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#define GFAR_MIIM_TBI_ANEX 0x6
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#define GFAR_MIIM_TBI_ANEX_NP 0x00000004
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#define GFAR_MIIM_TBI_ANEX_PRX 0x00000002
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#define GFAR_MIIM_GBIT_CONTROL 0x9
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#define GFAR_MIIM_GBIT_CONTROL_INIT 0xe00
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#define GFAR_MIIM_EXT_PAGE_ACCESS 0x1f
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#define GFAR_MIIM_GBIT_CON 0x09
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#define GFAR_MIIM_GBIT_CON_ADVERT 0x0e00
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#define GFAR_MIIM_READ_COMMAND 0x00000001
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#define MRBLR_INIT_SETTINGS 1536
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#define MINFLR_INIT_SETTINGS 0x00000040
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#define DMACTRL_INIT_SETTINGS 0x000000c3
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#define GFAR_DMACTRL_GRS 0x00000010
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#define GFAR_DMACTRL_GTS 0x00000008
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#define GFAR_TSTAT_CLEAR_THALT 0x80000000
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#define GFAR_RSTAT_CLEAR_RHALT 0x00800000
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#define GFAR_IEVENT_INIT_CLEAR 0xffffffff
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#define GFAR_IEVENT_BABR 0x80000000
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#define GFAR_IEVENT_RXC 0x40000000
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#define GFAR_IEVENT_BSY 0x20000000
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#define GFAR_IEVENT_EBERR 0x10000000
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#define GFAR_IEVENT_MSRO 0x04000000
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#define GFAR_IEVENT_GTSC 0x02000000
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#define GFAR_IEVENT_BABT 0x01000000
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#define GFAR_IEVENT_TXC 0x00800000
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#define GFAR_IEVENT_TXE 0x00400000
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#define GFAR_IEVENT_TXB 0x00200000
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#define GFAR_IEVENT_TXF 0x00100000
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#define GFAR_IEVENT_IE 0x00080000
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#define GFAR_IEVENT_LC 0x00040000
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#define GFAR_IEVENT_CRL 0x00020000
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#define GFAR_IEVENT_XFUN 0x00010000
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#define GFAR_IEVENT_RXB0 0x00008000
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#define GFAR_IEVENT_GRSC 0x00000100
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#define GFAR_IEVENT_RXF0 0x00000080
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#define GFAR_IMASK_INIT_CLEAR 0x00000000
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/* Default Attribute fields */
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#define ATTR_INIT_SETTINGS 0x000000c0
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#define ATTRELI_INIT_SETTINGS 0x00000000
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/* TxBD status field bits */
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#define TXBD_READY 0x8000
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#define TXBD_PADCRC 0x4000
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#define TXBD_WRAP 0x2000
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#define TXBD_INTERRUPT 0x1000
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#define TXBD_LAST 0x0800
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#define TXBD_CRC 0x0400
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#define TXBD_DEF 0x0200
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#define TXBD_HUGEFRAME 0x0080
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#define TXBD_LATECOLLISION 0x0080
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#define TXBD_RETRYLIMIT 0x0040
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#define TXBD_RETRYCOUNTMASK 0x003c
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#define TXBD_UNDERRUN 0x0002
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#define TXBD_STATS 0x03ff
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/* RxBD status field bits */
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#define RXBD_EMPTY 0x8000
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#define RXBD_RO1 0x4000
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#define RXBD_WRAP 0x2000
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#define RXBD_INTERRUPT 0x1000
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#define RXBD_LAST 0x0800
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#define RXBD_FIRST 0x0400
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#define RXBD_MISS 0x0100
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#define RXBD_BROADCAST 0x0080
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#define RXBD_MULTICAST 0x0040
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#define RXBD_LARGE 0x0020
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#define RXBD_NONOCTET 0x0010
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#define RXBD_SHORT 0x0008
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#define RXBD_CRCERR 0x0004
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#define RXBD_OVERRUN 0x0002
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#define RXBD_TRUNCATED 0x0001
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#define RXBD_STATS 0x003f
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struct txbd8 {
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ushort status; /* Status Fields */
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ushort length; /* Buffer length */
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uint bufPtr; /* Buffer Pointer */
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};
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struct rxbd8 {
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ushort status; /* Status Fields */
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ushort length; /* Buffer Length */
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uint bufPtr; /* Buffer Pointer */
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};
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/* eTSEC general control and status registers */
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#define GFAR_IEVENT_OFFSET 0x010 /* Interrupt Event */
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#define GFAR_IMASK_OFFSET 0x014 /* Interrupt Mask */
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#define GFAR_ECNTRL_OFFSET 0x020 /* Ethernet Control */
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#define GFAR_MINFLR_OFFSET 0x024 /* Minimum Frame Length */
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#define GFAR_DMACTRL_OFFSET 0x02c /* DMA Control */
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/* eTSEC transmit control and status register */
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#define GFAR_TSTAT_OFFSET 0x104 /* transmit status register */
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#define GFAR_TBASE0_OFFSET 0x204 /* TxBD Base Address */
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/* eTSEC receive control and status register */
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#define GFAR_RCTRL_OFFSET 0x300 /* Receive Control */
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#define GFAR_RSTAT_OFFSET 0x304 /* transmit status register */
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#define GFAR_MRBLR_OFFSET 0x340 /* Maximum Receive Buffer Length */
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#define GFAR_RBASE0_OFFSET 0x404 /* RxBD Base Address */
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/* eTSEC MAC registers */
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#define GFAR_MACCFG1_OFFSET 0x500 /* MAC Configuration #1 */
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#define GFAR_MACCFG2_OFFSET 0x504 /* MAC Configuration #2 */
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#define GFAR_MIIMCFG_OFFSET 0x520 /* MII management configuration */
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#define GFAR_MIIMCOM_OFFSET 0x524 /* MII management command */
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#define GFAR_MIIMADD_OFFSET 0x528 /* MII management address */
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#define GFAR_MIIMCON_OFFSET 0x52c /* MII management control */
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#define GFAR_MIIMSTAT_OFFSET 0x530 /* MII management status */
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#define GFAR_MIIMMIND_OFFSET 0x534 /* MII management indicator */
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#define GFAR_MACSTRADDR1_OFFSET 0x540 /* MAC station address #1 */
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#define GFAR_MACSTRADDR2_OFFSET 0x544 /* MAC station address #2 */
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/* eTSEC transmit and receive counters registers. */
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#define GFAR_TR64_OFFSET 0x680
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/* eTSEC counter control and TOE statistics registers */
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#define GFAR_CAM1_OFFSET 0x738
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#define GFAR_CAM2_OFFSET 0x73c
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/* Individual/group address registers */
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#define GFAR_IADDR0_OFFSET 0x800
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#define GFAR_IADDR1_OFFSET 0x804
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#define GFAR_IADDR2_OFFSET 0x808
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#define GFAR_IADDR3_OFFSET 0x80c
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#define GFAR_IADDR4_OFFSET 0x810
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#define GFAR_IADDR5_OFFSET 0x814
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#define GFAR_IADDR6_OFFSET 0x818
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#define GFAR_IADDR7_OFFSET 0x81c
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#define GFAR_IADDR(REGNUM) (GFAR_IADDR##REGNUM##_OFFSET)
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/* Group address registers */
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#define GFAR_GADDR0_OFFSET 0x880
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#define GFAR_GADDR1_OFFSET 0x884
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#define GFAR_GADDR2_OFFSET 0x888
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#define GFAR_GADDR3_OFFSET 0x88c
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#define GFAR_GADDR4_OFFSET 0x890
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#define GFAR_GADDR5_OFFSET 0x894
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#define GFAR_GADDR6_OFFSET 0x898
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#define GFAR_GADDR7_OFFSET 0x89c
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#define GFAR_GADDR(REGNUM) (GFAR_GADDR##REGNUM##_OFFSET)
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/* eTSEC DMA attributes registers */
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#define GFAR_ATTR_OFFSET 0xbf8 /* Default Attribute Register */
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#define GFAR_ATTRELI_OFFSET 0xbfc /* Default Attribute Extract Len/Idx */
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struct gfar_phy {
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void __iomem *regs;
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struct device_d *dev;
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struct mii_bus miibus;
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};
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struct gfar_private {
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struct eth_device edev;
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void __iomem *regs;
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int mdiobus_tbi;
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struct gfar_phy *gfar_mdio;
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struct gfar_phy *gfar_tbi;
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struct phy_info *phyinfo;
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volatile struct txbd8 *txbd;
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volatile struct rxbd8 *rxbd;
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uint txidx;
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uint rxidx;
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uint phyaddr;
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uint tbicr;
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uint tbiana;
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uint link;
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uint duplexity;
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uint speed;
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};
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#endif /* __GIANFAR_H */
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