237 lines
7.6 KiB
C
237 lines
7.6 KiB
C
/*
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* (C) Copyright 2014
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* Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on kirkwood_egiga driver from u-boot
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* based on - Driver for MV64360X ethernet ports
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* Copyright (C) 2002 rabeeh@galileo.co.il
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#ifndef __ORION_GBE_
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#define __ORION_GBE_
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/* Ethernet Unit Base Address */
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#define EUNIT_BA(x) (0x200 + (x) * 0x8)
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/* Ethernet Unit Size */
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#define EUNIT_S(x) (0x204 + (x) * 0x8)
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/* Ethernet Unit High Address */
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#define EUNIT_HA(x) (0x280 + (x) * 0x4)
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/* Ethernet Unit Base Address Enable */
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#define EUNIT_BARE 0x290
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/* Ethernet Unit Port Access Protect */
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#define EUNIT_PAP 0x294
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#define NO_ACCESS 0
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#define ACCESS_READ_ONLY 1
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#define ACCESS_FULL 3
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/* Port Registers Offset */
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#define PORTn_REGS(x) (0x400 + (x) * 0x400)
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/* Port Configuration */
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#define PORT_C 0x000
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#define PROMISCUOUS_MODE BIT(0)
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#define DEFAULT_RXQ(x) ((x) << 1)
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#define DEFAULT_ARPQ(x) ((x) << 4)
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#define BCAST_OTHER_REJECT BIT(7)
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#define BCAST_IP_REJECT BIT(8)
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#define BCAST_ARP_REJECT BIT(9)
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#define AUTO_SET_NO_TX_ERR BIT(12)
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#define TCPQ_CAPTURE_ENABLE BIT(14)
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#define UDPQ_CAPTURE_ENABLE BIT(15)
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#define DEFAULT_TCPQ(x) ((x) << 16)
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#define DEFAULT_UDPQ(x) ((x) << 19)
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#define DEFAULT_BPDUQ(x) ((x) << 22)
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#define RX_TCP_CHKSUM_HEADER BIT(25)
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/* Port Configuration Extended */
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#define PORT_CX 0x004
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#define TX_CRC_GEN_DISABLE BIT(3)
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#define BPDUQ_CAPTURE_ENABLE BIT(0)
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/* Port MAC Address High */
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#define PORT_MACAL 0x014
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/* Port MAC Address Low */
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#define PORT_MACAH 0x018
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/* Port SDMA Configuration */
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#define PORT_SDC 0x01c
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#define TX_BURST_SIZE_1 (0 << 22)
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#define TX_BURST_SIZE_2 (1 << 22)
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#define TX_BURST_SIZE_4 (2 << 22)
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#define TX_BURST_SIZE_8 (3 << 22)
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#define TX_BURST_SIZE_16 (4 << 22)
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#define TX_BLM_SWAP (0 << 5)
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#define TX_BLM_NO_SWAP (1 << 5)
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#define RX_BLM_SWAP (0 << 4)
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#define RX_BLM_NO_SWAP (1 << 4)
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#define RX_BURST_SIZE_1 (0 << 1)
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#define RX_BURST_SIZE_2 (1 << 1)
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#define RX_BURST_SIZE_4 (2 << 1)
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#define RX_BURST_SIZE_8 (3 << 1)
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#define RX_BURST_SIZE_16 (4 << 1)
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/* Port Serial Control 0 */
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#define PORT_SC0 0x03c
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#define SC0_RESERVED BIT(9)
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#define PORT_ENABLE BIT(0)
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#define FORCE_LINK_PASS BIT(1)
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#define DISABLE_ANEG_DUPLEX BIT(2)
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#define DISABLE_ANEG_FLOWCTRL BIT(3)
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#define ADVERTISE_PAUSE BIT(4)
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#define FORCE_FLOWCTRL_OFF (0 << 5)
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#define FORCE_FLOWCTRL_ON (1 << 5)
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#define FORCE_FLOWCTRL_MASK (3 << 5)
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#define FORCE_BACKPRESS_NO_JAM (0 << 7)
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#define FORCE_BACKPRESS_JAM (1 << 7)
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#define FORCE_BACKPRESS_MASK (3 << 7)
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#define FORCE_NO_LINK_FAIL BIT(10)
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#define DISABLE_ANEG_SPEED BIT(13)
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#define ADVERTISE_DTE BIT(14)
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#define MII_PHY_MODE BIT(15)
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#define MII_SRC_SYNCHRONOUS BIT(16)
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#define MRU_1518 (0 << 17)
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#define MRU_1522 (1 << 17)
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#define MRU_1552 (2 << 17)
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#define MRU_9022 (3 << 17)
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#define MRU_9192 (4 << 17)
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#define MRU_9700 (5 << 17)
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#define MRU_MASK (7 << 17)
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#define SET_FULL_DUPLEX BIT(21)
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#define SET_FLOWCTRL_ENABLE BIT(22)
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#define SET_SPEED_1000 (1 << 23)
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#define SET_SPEED_10 (0 << 23)
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#define SET_SPEED_100 (2 << 23)
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#define SET_SPEED_MASK (3 << 23)
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/* Port Status 0 */
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#define PORT_S0 0x044
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/* Port Trasmit Queue Command */
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#define PORT_TQC 0x048
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/* Port Serial Control 1 */
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#define PORT_SC1 0x04c
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#define SC1_RESERVED (0x2 << 9)
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#define LOOPBACK_PCS BIT(1)
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#define RGMII_ENABLE BIT(3)
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#define PORT_RESET BIT(4)
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#define CLK125_BYPASS BIT(5)
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#define INBAND_ANEG BIT(6)
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#define INBAND_ANEG_BYPASS BIT(7)
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#define INBAND_ANEG_RESTART BIT(8)
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#define LIMIT_TO_1000BASEX BIT(11)
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#define COL_ON_BACKPRESS BIT(15)
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#define COL_LIMIT(x) (((x) & 0xfff) << 16)
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#define DEFAULT_COL_LIMIT COL_LIMIT(0x23)
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#define COL_ON_BACKPRESS BIT(15)
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#define EN_MII_ODD_PREAMBLE BIT(22)
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/* Port Status 1 */
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#define PORT_S1 0x050
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/* Port Interrupt Cause */
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#define PORT_IC 0x060
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/* Port Interrupt Mask */
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#define PORT_IM 0x068
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#define INT_SUM BIT(31)
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#define TX_END BIT(19)
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#define RXQ_ERR (15 << 11)
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#define RX_ERR BIT(10)
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#define TXQ_ERR (15 << 2)
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#define EXTENDED_INT BIT(1)
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#define RX_RETURN BIT(0)
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/* Port Extended Interrupt Cause */
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#define PORT_EIC 0x064
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/* Port Extended Interrupt Mask */
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#define PORT_EIM 0x06c
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#define EXTENDED_INT_SUM BIT(31)
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#define PRBS_ERR BIT(25)
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#define INTERNAL_ADDR_ERR BIT(23)
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#define LINK_CHANGE BIT(20)
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#define TX_UNDERRUN BIT(19)
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#define RX_OVERRUN BIT(18)
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#define PHY_CHANGE BIT(16)
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#define TX_ERR BIT(8)
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#define TX_RETURN BIT(0)
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/* Port Maximum Transmit Unit */
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#define PORT_MTU 0x0e8
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/* Port Current Receive Descriptor Pointer */
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#define PORT_CRDP(x) (0x20c + (x) * 0x10)
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/* Port Receive Queue Command */
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#define PORT_RQC 0x280
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/* Port Transmit Current Queue Descriptor Pointer */
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#define PORT_TCQDP(x) (0x2c0 + (x) * 0x04)
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/* Port Transmit Queue Token Bucket Counter */
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#define PORT_TQTBCNT(x) (0x300 + (x) * 0x10)
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/* Port Transmit Queue Token Bucket Configuration */
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#define PORT_TQTBC(x) (0x304 + (x) * 0x10)
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#define PORT_DFSMT(x) (0x1000 + ((x) * 0x04))
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#define PORT_DFOMT(x) (0x1100 + ((x) * 0x04))
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#define PORT_DFUT(x) (0x1200 + ((x) * 0x04))
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#define DFT_ENTRY_MASK 0xff
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#define DFT_ENTRY_SIZE 8
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#define DFT_QUEUE_SHIFT 1
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#define DFT_PASS BIT(0)
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#define RXDESC_ERROR BIT(0)
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#define RXDESC_ERROR_CRC (0 << 1)
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#define RXDESC_ERROR_OVERRUN (1 << 1)
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#define RXDESC_ERROR_MAXLEN (2 << 1)
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#define RXDESC_ERROR_RESOURCE (3 << 1)
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#define RXDESC_ERROR_MASK (3 << 1)
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#define RXDESC_ERROR_SHIFT 1
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#define RXDESC_L4_CHECKSUM(x) (((x) & (0xffff << 3)) >> 3)
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#define RXDESC_VLAN_TAGGED BIT(19)
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#define RXDESC_BDPU BIT(20)
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#define RXDESC_FRAME_TCP (0 << 21)
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#define RXDESC_FRAME_UDP (1 << 21)
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#define RXDESC_FRAME_OTHER (2 << 21)
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#define RXDESC_FRAME_MASK (3 << 21)
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#define RXDESC_L2_IS_ETHERNET BIT(23)
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#define RXDESC_L4_IS_IPV4 BIT(24)
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#define RXDESC_L4_HEADER_OK BIT(25)
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#define RXDESC_LAST BIT(26)
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#define RXDESC_FIRST BIT(27)
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#define RXDESC_UNKNOWN_DEST BIT(28)
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#define RXDESC_ENABLE_IRQ BIT(29)
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#define RXDESC_L4_CHECKSUM_OK BIT(30)
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#define RXDESC_OWNED_BY_DMA BIT(31)
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#define RXDESC_BYTECOUNT_FRAG BIT(2)
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#define TXDESC_ERROR BIT(0)
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#define TXDESC_ERROR_LATE_COLL (0 << 1)
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#define TXDESC_ERROR_UNDERRUN (1 << 1)
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#define TXDESC_ERROR_RET_LIMIT (2 << 1)
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#define TXDESC_ERROR_MASK (3 << 1)
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#define TXDESC_ERROR_SHIFT 1
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#define TXDESC_LCC_SNAP BIT(9)
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#define TXDESC_L4_CHK_FIRST BIT(10)
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#define TXDESC_IPV4_HEADER_LEN(x) (((x) & 0xf) << 11)
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#define TXDESC_VLAN_TAGGED BIT(15)
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#define TXDESC_FRAME_TCP (0 << 16)
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#define TXDESC_FRAME_UDP (1 << 16)
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#define TXDESC_GEN_FRAME_CHECKSUM BIT(17)
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#define TXDESC_GEN_IPV4_CHECKSUM BIT(18)
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#define TXDESC_ZERO_PADDING BIT(19)
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#define TXDESC_LAST BIT(20)
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#define TXDESC_FIRST BIT(21)
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#define TXDESC_GEN_CRC BIT(22) /* Orion5x only */
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#define TXDESC_ENABLE_IRQ BIT(23)
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#define TXDESC_NO_AUTO_RETURN BIT(30)
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#define TXDESC_OWNED_BY_DMA BIT(31)
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#endif
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