735 lines
25 KiB
C
735 lines
25 KiB
C
/*
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* Copyright 2010-2011 Calxeda, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <net.h>
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#include <clock.h>
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#include <malloc.h>
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#include <xfuncs.h>
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#include <init.h>
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#include <errno.h>
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#include <io.h>
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#include <linux/err.h>
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#include <asm/mmu.h>
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#define TX_NUM_DESC 1
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#define RX_NUM_DESC 32
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#define ETH_BUF_SZ 2048
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#define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
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#define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
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/* XGMAC Register definitions */
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#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
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#define XGMAC_FRAME_FILTER 0x00000004 /* MAC Frame Filter */
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#define XGMAC_FLOW_CTRL 0x00000018 /* MAC Flow Control */
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#define XGMAC_VLAN_TAG 0x0000001C /* VLAN Tags */
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#define XGMAC_VERSION 0x00000020 /* Version */
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#define XGMAC_VLAN_INCL 0x00000024 /* VLAN tag for tx frames */
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#define XGMAC_LPI_CTRL 0x00000028 /* LPI Control and Status */
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#define XGMAC_LPI_TIMER 0x0000002C /* LPI Timers Control */
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#define XGMAC_TX_PACE 0x00000030 /* Transmit Pace and Stretch */
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#define XGMAC_VLAN_HASH 0x00000034 /* VLAN Hash Table */
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#define XGMAC_DEBUG 0x00000038 /* Debug */
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#define XGMAC_INT_STAT 0x0000003C /* Interrupt and Control */
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#define XGMAC_ADDR_HIGH(reg) (0x00000040 + ((reg) * 8))
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#define XGMAC_ADDR_LOW(reg) (0x00000044 + ((reg) * 8))
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#define XGMAC_HASH(n) (0x00000300 + (n) * 4) /* HASH table regs */
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#define XGMAC_NUM_HASH 16
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#define XGMAC_OMR 0x00000400
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#define XGMAC_REMOTE_WAKE 0x00000700 /* Remote Wake-Up Frm Filter */
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#define XGMAC_PMT 0x00000704 /* PMT Control and Status */
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#define XGMAC_MMC_CTRL 0x00000800 /* XGMAC MMC Control */
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#define XGMAC_MMC_INTR_RX 0x00000804 /* Recieve Interrupt */
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#define XGMAC_MMC_INTR_TX 0x00000808 /* Transmit Interrupt */
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#define XGMAC_MMC_INTR_MASK_RX 0x0000080c /* Recieve Interrupt Mask */
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#define XGMAC_MMC_INTR_MASK_TX 0x00000810 /* Transmit Interrupt Mask */
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/* Hardware TX Statistics Counters */
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#define XGMAC_MMC_TXOCTET_GB_LO 0x00000814
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#define XGMAC_MMC_TXOCTET_GB_HI 0x00000818
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#define XGMAC_MMC_TXFRAME_GB_LO 0x0000081C
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#define XGMAC_MMC_TXFRAME_GB_HI 0x00000820
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#define XGMAC_MMC_TXBCFRAME_G 0x00000824
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#define XGMAC_MMC_TXMCFRAME_G 0x0000082C
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#define XGMAC_MMC_TXUCFRAME_GB 0x00000864
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#define XGMAC_MMC_TXMCFRAME_GB 0x0000086C
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#define XGMAC_MMC_TXBCFRAME_GB 0x00000874
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#define XGMAC_MMC_TXUNDERFLOW 0x0000087C
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#define XGMAC_MMC_TXOCTET_G_LO 0x00000884
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#define XGMAC_MMC_TXOCTET_G_HI 0x00000888
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#define XGMAC_MMC_TXFRAME_G_LO 0x0000088C
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#define XGMAC_MMC_TXFRAME_G_HI 0x00000890
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#define XGMAC_MMC_TXPAUSEFRAME 0x00000894
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#define XGMAC_MMC_TXVLANFRAME 0x0000089C
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/* Hardware RX Statistics Counters */
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#define XGMAC_MMC_RXFRAME_GB_LO 0x00000900
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#define XGMAC_MMC_RXFRAME_GB_HI 0x00000904
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#define XGMAC_MMC_RXOCTET_GB_LO 0x00000908
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#define XGMAC_MMC_RXOCTET_GB_HI 0x0000090C
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#define XGMAC_MMC_RXOCTET_G_LO 0x00000910
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#define XGMAC_MMC_RXOCTET_G_HI 0x00000914
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#define XGMAC_MMC_RXBCFRAME_G 0x00000918
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#define XGMAC_MMC_RXMCFRAME_G 0x00000920
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#define XGMAC_MMC_RXCRCERR 0x00000928
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#define XGMAC_MMC_RXRUNT 0x00000930
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#define XGMAC_MMC_RXJABBER 0x00000934
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#define XGMAC_MMC_RXUCFRAME_G 0x00000970
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#define XGMAC_MMC_RXLENGTHERR 0x00000978
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#define XGMAC_MMC_RXPAUSEFRAME 0x00000988
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#define XGMAC_MMC_RXOVERFLOW 0x00000990
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#define XGMAC_MMC_RXVLANFRAME 0x00000998
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#define XGMAC_MMC_RXWATCHDOG 0x000009a0
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/* DMA Control and Status Registers */
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#define XGMAC_DMA_BUS_MODE 0x00000f00 /* Bus Mode */
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#define XGMAC_DMA_TX_POLL 0x00000f04 /* Transmit Poll Demand */
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#define XGMAC_DMA_RX_POLL 0x00000f08 /* Received Poll Demand */
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#define XGMAC_DMA_RX_BASE_ADDR 0x00000f0c /* Receive List Base */
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#define XGMAC_DMA_TX_BASE_ADDR 0x00000f10 /* Transmit List Base */
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#define XGMAC_DMA_STATUS 0x00000f14 /* Status Register */
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#define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
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#define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
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#define XGMAC_DMA_MISS_FRAME_CTR 0x00000f20 /* Missed Frame Counter */
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#define XGMAC_DMA_RI_WDOG_TIMER 0x00000f24 /* RX Intr Watchdog Timer */
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#define XGMAC_DMA_AXI_BUS 0x00000f28 /* AXI Bus Mode */
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#define XGMAC_DMA_AXI_STATUS 0x00000f2C /* AXI Status */
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#define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
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#define XGMAC_ADDR_AE 0x80000000
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#define XGMAC_MAX_FILTER_ADDR 31
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/* PMT Control and Status */
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#define XGMAC_PMT_POINTER_RESET 0x80000000
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#define XGMAC_PMT_GLBL_UNICAST 0x00000200
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#define XGMAC_PMT_WAKEUP_RX_FRM 0x00000040
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#define XGMAC_PMT_MAGIC_PKT 0x00000020
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#define XGMAC_PMT_WAKEUP_FRM_EN 0x00000004
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#define XGMAC_PMT_MAGIC_PKT_EN 0x00000002
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#define XGMAC_PMT_POWERDOWN 0x00000001
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#define XGMAC_CONTROL_SPD 0x40000000 /* Speed control */
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#define XGMAC_CONTROL_SPD_MASK 0x60000000
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#define XGMAC_CONTROL_SPD_1G 0x60000000
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#define XGMAC_CONTROL_SPD_2_5G 0x40000000
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#define XGMAC_CONTROL_SPD_10G 0x00000000
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#define XGMAC_CONTROL_SARC 0x10000000 /* Source Addr Insert/Replace */
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#define XGMAC_CONTROL_SARK_MASK 0x18000000
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#define XGMAC_CONTROL_CAR 0x04000000 /* CRC Addition/Replacement */
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#define XGMAC_CONTROL_CAR_MASK 0x06000000
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#define XGMAC_CONTROL_DP 0x01000000 /* Disable Padding */
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#define XGMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on rx */
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#define XGMAC_CONTROL_JD 0x00400000 /* Jabber disable */
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#define XGMAC_CONTROL_JE 0x00100000 /* Jumbo frame */
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#define XGMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
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#define XGMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */
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#define XGMAC_CONTROL_ACS 0x00000080 /* Automatic Pad/FCS Strip */
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#define XGMAC_CONTROL_DDIC 0x00000010 /* Disable Deficit Idle Count */
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#define XGMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */
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#define XGMAC_CONTROL_RE 0x00000004 /* Receiver Enable */
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/* XGMAC Frame Filter defines */
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#define XGMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */
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#define XGMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */
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#define XGMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */
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#define XGMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */
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#define XGMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */
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#define XGMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */
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#define XGMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */
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#define XGMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */
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#define XGMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */
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#define XGMAC_FRAME_FILTER_VHF 0x00000800 /* VLAN Hash Filter */
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#define XGMAC_FRAME_FILTER_VPF 0x00001000 /* VLAN Perfect Filter */
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#define XGMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */
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#define FIFO_MINUS_1K 0x0
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#define FIFO_MINUS_2K 0x1
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#define FIFO_MINUS_3K 0x2
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#define FIFO_MINUS_4K 0x3
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#define FIFO_MINUS_6K 0x4
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#define FIFO_MINUS_8K 0x5
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#define FIFO_MINUS_12K 0x6
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#define FIFO_MINUS_16K 0x7
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/* XGMAC FLOW CTRL defines */
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#define XGMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */
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#define XGMAC_FLOW_CTRL_PT_SHIFT 16
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#define XGMAC_FLOW_CTRL_DZQP 0x00000080 /* Disable Zero-Quanta Phase */
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#define XGMAC_FLOW_CTRL_PLT 0x00000020 /* Pause Low Threshhold */
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#define XGMAC_FLOW_CTRL_PLT_SHIFT 4
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#define XGMAC_FLOW_CTRL_PLT_MASK 0x00000030 /* PLT MASK */
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#define XGMAC_FLOW_CTRL_UP 0x00000008 /* Unicast Pause Frame Detect */
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#define XGMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */
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#define XGMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */
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#define XGMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */
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/* XGMAC_INT_STAT reg */
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#define XGMAC_INT_STAT_PMT 0x0080 /* PMT Interrupt Status */
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#define XGMAC_INT_STAT_LPI 0x0040 /* LPI Interrupt Status */
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/* DMA Bus Mode register defines */
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#define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */
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#define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */
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#define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */
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#define DMA_BUS_MODE_ATDS 0x00000080 /* Alternate Descriptor Size */
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/* Programmable burst length */
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#define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
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#define DMA_BUS_MODE_PBL_SHIFT 8
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#define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
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#define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
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#define DMA_BUS_MODE_RPBL_SHIFT 17
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#define DMA_BUS_MODE_USP 0x00800000
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#define DMA_BUS_MODE_8PBL 0x01000000
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#define DMA_BUS_MODE_AAL 0x02000000
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#define DMA_AXIMODE_ENLPI 0x80000000
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#define DMA_AXIMODE_MGK 0x40000000
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#define DMA_AXIMODE_WROSR 0x00100000
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#define DMA_AXIMODE_WROSR_MASK 0x00F00000
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#define DMA_AXIMODE_WROSR_SHIFT 20
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#define DMA_AXIMODE_RDOSR 0x00010000
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#define DMA_AXIMODE_RDOSR_MASK 0x000F0000
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#define DMA_AXIMODE_RDOSR_SHIFT 16
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#define DMA_AXIMODE_AAL 0x00001000
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#define DMA_AXIMODE_BLEN256 0x00000080
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#define DMA_AXIMODE_BLEN128 0x00000040
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#define DMA_AXIMODE_BLEN64 0x00000020
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#define DMA_AXIMODE_BLEN32 0x00000010
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#define DMA_AXIMODE_BLEN16 0x00000008
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#define DMA_AXIMODE_BLEN8 0x00000004
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#define DMA_AXIMODE_BLEN4 0x00000002
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#define DMA_AXIMODE_UNDEF 0x00000001
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/* DMA Bus Mode register defines */
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#define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */
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#define DMA_BUS_PR_RATIO_SHIFT 14
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#define DMA_BUS_FB 0x00010000 /* Fixed Burst */
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/* DMA Control register defines */
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#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
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#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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#define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
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/* DMA Normal interrupt */
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#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
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#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
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#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
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#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
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#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
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#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
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#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
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#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
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#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
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#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
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#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
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#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavail */
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#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
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#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
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#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
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DMA_INTR_ENA_TUE)
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#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
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DMA_INTR_ENA_RWE | DMA_INTR_ENA_RSE | \
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DMA_INTR_ENA_RUE | DMA_INTR_ENA_UNE | \
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DMA_INTR_ENA_OVE | DMA_INTR_ENA_TJE | \
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DMA_INTR_ENA_TSE)
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/* DMA default interrupt mask */
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#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
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/* DMA Status register defines */
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#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
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#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
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#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
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#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
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#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
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#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
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#define DMA_STATUS_TS_SHIFT 20
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#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
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#define DMA_STATUS_RS_SHIFT 17
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#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
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#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
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#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
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#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
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#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
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#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
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#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
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#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
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#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
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#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
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#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
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#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
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#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavail */
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#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
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#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
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/* Common MAC defines */
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#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
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#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
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/* XGMAC Operation Mode Register */
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#define XGMAC_OMR_TSF 0x00200000 /* TX FIFO Store and Forward */
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#define XGMAC_OMR_FTF 0x00100000 /* Flush Transmit FIFO */
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#define XGMAC_OMR_TTC 0x00020000 /* Transmit Threshhold Ctrl */
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#define XGMAC_OMR_TTC_SHIFT 16
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#define XGMAC_OMR_TTC_MASK 0x00030000
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#define XGMAC_OMR_RFD 0x00006000 /* FC Deactivation Threshhold */
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#define XGMAC_OMR_RFD_SHIFT 12
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#define XGMAC_OMR_RFD_MASK 0x00007000 /* FC Deact Threshhold MASK */
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#define XGMAC_OMR_RFA 0x00000600 /* FC Activation Threshhold */
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#define XGMAC_OMR_RFA_SHIFT 9
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#define XGMAC_OMR_RFA_MASK 0x00000E00 /* FC Act Threshhold MASK */
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#define XGMAC_OMR_EFC 0x00000100 /* Enable Hardware FC */
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#define XGMAC_OMR_FEF 0x00000080 /* Forward Error Frames */
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#define XGMAC_OMR_DT 0x00000040 /* Drop TCP/IP csum Errors */
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#define XGMAC_OMR_RSF 0x00000020 /* RX FIFO Store and Forward */
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#define XGMAC_OMR_RTC_256 0x00000018 /* RX Threshhold Ctrl */
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#define XGMAC_OMR_RTC_MASK 0x00000018 /* RX Threshhold Ctrl MASK */
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/* XGMAC HW Features Register */
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#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* TX Checksum offload */
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#define XGMAC_MMC_CTRL_CNT_FRZ 0x00000008
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/* XGMAC Descriptor Defines */
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#define MAX_DESC_BUF_SZ (0x2000 - 8)
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#define RXDESC_EXT_STATUS 0x00000001
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#define RXDESC_CRC_ERR 0x00000002
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#define RXDESC_RX_ERR 0x00000008
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#define RXDESC_RX_WDOG 0x00000010
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#define RXDESC_FRAME_TYPE 0x00000020
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#define RXDESC_GIANT_FRAME 0x00000080
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#define RXDESC_LAST_SEG 0x00000100
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#define RXDESC_FIRST_SEG 0x00000200
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#define RXDESC_VLAN_FRAME 0x00000400
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#define RXDESC_OVERFLOW_ERR 0x00000800
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#define RXDESC_LENGTH_ERR 0x00001000
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#define RXDESC_SA_FILTER_FAIL 0x00002000
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#define RXDESC_DESCRIPTOR_ERR 0x00004000
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#define RXDESC_ERROR_SUMMARY 0x00008000
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#define RXDESC_FRAME_LEN_OFFSET 16
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#define RXDESC_FRAME_LEN_MASK 0x3fff0000
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#define RXDESC_DA_FILTER_FAIL 0x40000000
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#define RXDESC1_END_RING 0x00008000
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#define RXDESC_IP_PAYLOAD_MASK 0x00000003
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#define RXDESC_IP_PAYLOAD_UDP 0x00000001
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#define RXDESC_IP_PAYLOAD_TCP 0x00000002
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#define RXDESC_IP_PAYLOAD_ICMP 0x00000003
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#define RXDESC_IP_HEADER_ERR 0x00000008
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#define RXDESC_IP_PAYLOAD_ERR 0x00000010
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#define RXDESC_IPV4_PACKET 0x00000040
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#define RXDESC_IPV6_PACKET 0x00000080
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#define TXDESC_UNDERFLOW_ERR 0x00000001
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#define TXDESC_JABBER_TIMEOUT 0x00000002
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#define TXDESC_LOCAL_FAULT 0x00000004
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#define TXDESC_REMOTE_FAULT 0x00000008
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#define TXDESC_VLAN_FRAME 0x00000010
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#define TXDESC_FRAME_FLUSHED 0x00000020
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#define TXDESC_IP_HEADER_ERR 0x00000040
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#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
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#define TXDESC_ERROR_SUMMARY 0x00008000
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#define TXDESC_SA_CTRL_INSERT 0x00040000
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#define TXDESC_SA_CTRL_REPLACE 0x00080000
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#define TXDESC_2ND_ADDR_CHAINED 0x00100000
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#define TXDESC_END_RING 0x00200000
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#define TXDESC_CSUM_IP 0x00400000
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#define TXDESC_CSUM_IP_PAYLD 0x00800000
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#define TXDESC_CSUM_ALL 0x00C00000
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#define TXDESC_CRC_EN_REPLACE 0x01000000
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#define TXDESC_CRC_EN_APPEND 0x02000000
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#define TXDESC_DISABLE_PAD 0x04000000
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#define TXDESC_FIRST_SEG 0x10000000
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#define TXDESC_LAST_SEG 0x20000000
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#define TXDESC_INTERRUPT 0x40000000
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#define DESC_OWN 0x80000000
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#define DESC_BUFFER1_SZ_MASK 0x00001fff
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#define DESC_BUFFER2_SZ_MASK 0x1fff0000
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#define DESC_BUFFER2_SZ_OFFSET 16
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struct xgmac_dma_desc {
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__le32 flags;
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__le32 buf_size;
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__le32 buf1_addr; /* Buffer 1 Address Pointer */
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__le32 buf2_addr; /* Buffer 2 Address Pointer */
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__le32 ext_status;
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__le32 res[3];
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};
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struct xgmac_priv {
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struct xgmac_dma_desc *rx_chain;
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struct xgmac_dma_desc *tx_chain;
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char *rxbuffer;
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u32 tx_currdesc;
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u32 rx_currdesc;
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void __iomem *base;
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struct eth_device edev;
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struct device_d *dev;
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};
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/* XGMAC Descriptor Access Helpers */
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static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
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{
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if (buf_sz > MAX_DESC_BUF_SZ)
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p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
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(buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
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else
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p->buf_size = cpu_to_le32(buf_sz);
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}
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static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
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{
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u32 len = le32_to_cpu(p->buf_size);
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return (len & DESC_BUFFER1_SZ_MASK) +
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((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
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}
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static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
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int buf_sz)
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{
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struct xgmac_dma_desc *end = p + ring_size - 1;
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memset(p, 0, sizeof(*p) * ring_size);
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for (; p <= end; p++)
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desc_set_buf_len(p, buf_sz);
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end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
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}
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static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
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{
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memset(p, 0, sizeof(*p) * ring_size);
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p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
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}
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static inline int desc_get_owner(struct xgmac_dma_desc *p)
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{
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return le32_to_cpu(p->flags) & DESC_OWN;
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}
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static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
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{
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/* Clear all fields and set the owner */
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p->flags = cpu_to_le32(DESC_OWN);
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}
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static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
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{
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u32 tmpflags = le32_to_cpu(p->flags);
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tmpflags &= TXDESC_END_RING;
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tmpflags |= flags | DESC_OWN;
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p->flags = cpu_to_le32(tmpflags);
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}
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static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
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{
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return (void *)le32_to_cpu(p->buf1_addr);
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}
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static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
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void *paddr, int len)
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{
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p->buf1_addr = cpu_to_le32(paddr);
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if (len > MAX_DESC_BUF_SZ)
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p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
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}
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static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
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void *paddr, int len)
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{
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desc_set_buf_len(p, len);
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desc_set_buf_addr(p, paddr, len);
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}
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static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
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{
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u32 data = le32_to_cpu(p->flags);
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u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
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if (data & RXDESC_FRAME_TYPE)
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len -= 4;
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return len;
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}
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/*
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* Initialize a descriptor ring. Calxeda XGMAC is configured to use
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* advanced descriptors.
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*/
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static void init_rx_desc(struct xgmac_priv *priv)
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{
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struct xgmac_dma_desc *rxdesc = priv->rx_chain;
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void *rxbuffer = priv->rxbuffer;
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int i;
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desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
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writel((ulong)rxdesc, priv->base + XGMAC_DMA_RX_BASE_ADDR);
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for (i = 0; i < RX_NUM_DESC; i++) {
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desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
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ETH_BUF_SZ);
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desc_set_rx_owner(rxdesc + i);
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}
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}
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static void init_tx_desc(struct xgmac_priv *priv)
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{
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desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
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writel((ulong)priv->tx_chain, priv->base + XGMAC_DMA_TX_BASE_ADDR);
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}
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static int xgmac_reset(struct eth_device *dev)
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{
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struct xgmac_priv *priv = dev->priv;
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int ret;
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u32 value;
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value = readl(priv->base + XGMAC_CONTROL) & XGMAC_CONTROL_SPD_MASK;
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writel(DMA_BUS_MODE_SFT_RESET, priv->base + XGMAC_DMA_BUS_MODE);
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ret = wait_on_timeout(100 * MSECOND,
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!(readl(priv->base + XGMAC_DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET));
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writel(value, priv->base + XGMAC_CONTROL);
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return ret;
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}
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static int xgmac_open(struct eth_device *edev)
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{
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struct xgmac_priv *priv = edev->priv;
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int value;
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int ret;
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ret = xgmac_reset(edev);
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if (ret)
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return ret;
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/* set the AXI bus modes */
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value = DMA_BUS_MODE_ATDS |
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(16 << DMA_BUS_MODE_PBL_SHIFT) |
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DMA_BUS_MODE_FB | DMA_BUS_MODE_AAL;
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writel(value, priv->base + XGMAC_DMA_BUS_MODE);
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value = DMA_AXIMODE_AAL | DMA_AXIMODE_BLEN16 |
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DMA_AXIMODE_BLEN8 | DMA_AXIMODE_BLEN4;
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writel(value, priv->base + XGMAC_DMA_AXI_BUS);
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/* set flow control parameters and store and forward mode */
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value = (FIFO_MINUS_12K << XGMAC_OMR_RFD_SHIFT) |
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(FIFO_MINUS_4K << XGMAC_OMR_RFA_SHIFT) |
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XGMAC_OMR_EFC | XGMAC_OMR_TSF | XGMAC_OMR_RSF;
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writel(value, priv->base + XGMAC_OMR);
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/* enable pause frames */
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value = (1024 << XGMAC_FLOW_CTRL_PT_SHIFT) |
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(1 << XGMAC_FLOW_CTRL_PLT_SHIFT) |
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XGMAC_FLOW_CTRL_UP | XGMAC_FLOW_CTRL_RFE | XGMAC_FLOW_CTRL_TFE;
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writel(value, priv->base + XGMAC_FLOW_CTRL);
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/* Initialize the descriptor chains */
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init_rx_desc(priv);
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init_tx_desc(priv);
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/* must set to 0, or when started up will cause issues */
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priv->tx_currdesc = 0;
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priv->rx_currdesc = 0;
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/* set default core values */
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value = readl(priv->base + XGMAC_CONTROL);
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value &= XGMAC_CONTROL_SPD_MASK;
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value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
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XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
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/* Everything is ready enable both mac and DMA */
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value |= XGMAC_CONTROL_RE | XGMAC_CONTROL_TE;
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writel(value, priv->base + XGMAC_CONTROL);
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value = readl(priv->base + XGMAC_DMA_CONTROL);
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value |= DMA_CONTROL_SR | DMA_CONTROL_ST;
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writel(value, priv->base + XGMAC_DMA_CONTROL);
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return 0;
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}
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static int xgmac_send(struct eth_device *edev, void *packet, int length)
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{
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struct xgmac_priv *priv = edev->priv;
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u32 currdesc = priv->tx_currdesc;
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struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
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int ret;
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dma_flush_range((ulong) packet, (ulong)packet + length);
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desc_set_buf_addr_and_size(txdesc, packet, length);
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desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
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TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
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/* write poll demand */
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writel(1, priv->base + XGMAC_DMA_TX_POLL);
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ret = wait_on_timeout(1 * SECOND, !desc_get_owner(txdesc));
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if (ret) {
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dev_err(priv->dev, "TX timeout\n");
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return ret;
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}
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priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
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return 0;
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}
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static int xgmac_recv(struct eth_device *edev)
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{
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struct xgmac_priv *priv = edev->priv;
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u32 currdesc = priv->rx_currdesc;
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struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
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int length = 0;
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/* check if the host has the desc */
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if (desc_get_owner(rxdesc))
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return -1; /* something bad happened */
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length = desc_get_rx_frame_len(rxdesc);
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net_receive(edev, desc_get_buf_addr(rxdesc), length);
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/* set descriptor back to owned by XGMAC */
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desc_set_rx_owner(rxdesc);
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writel(1, priv->base + XGMAC_DMA_RX_POLL);
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priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
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return length;
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}
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static void xgmac_halt(struct eth_device *edev)
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{
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struct xgmac_priv *priv = edev->priv;
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int value;
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/* Disable TX/RX */
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value = readl(priv->base + XGMAC_CONTROL);
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value &= ~(XGMAC_CONTROL_RE | XGMAC_CONTROL_TE);
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writel(value, priv->base + XGMAC_CONTROL);
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/* Disable DMA */
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value = readl(priv->base + XGMAC_DMA_CONTROL);
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value &= ~(DMA_CONTROL_SR | DMA_CONTROL_ST);
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writel(value, priv->base + XGMAC_DMA_CONTROL);
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/* must set to 0, or when started up will cause issues */
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priv->tx_currdesc = 0;
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priv->rx_currdesc = 0;
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}
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static int xgmac_get_ethaddr(struct eth_device *edev, unsigned char *addr)
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{
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struct xgmac_priv *priv = edev->priv;
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u32 hi_addr, lo_addr;
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/* Read the MAC address from the hardware */
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hi_addr = readl(priv->base + XGMAC_ADDR_HIGH(0));
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lo_addr = readl(priv->base + XGMAC_ADDR_LOW(0));
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/* Extract the MAC address from the high and low words */
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addr[0] = lo_addr & 0xff;
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addr[1] = (lo_addr >> 8) & 0xff;
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addr[2] = (lo_addr >> 16) & 0xff;
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addr[3] = (lo_addr >> 24) & 0xff;
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addr[4] = hi_addr & 0xff;
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addr[5] = (hi_addr >> 8) & 0xff;
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return 0;
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}
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static int xgmac_set_ethaddr(struct eth_device *dev, unsigned char *addr)
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{
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struct xgmac_priv *priv = dev->priv;
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u32 data;
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data = (addr[5] << 8) | addr[4];
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writel(data, priv->base + XGMAC_ADDR_HIGH(0));
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data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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writel(data, priv->base + XGMAC_ADDR_LOW(0));
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return 0;
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}
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static int hb_xgmac_probe(struct device_d *dev)
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{
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struct eth_device *edev;
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struct xgmac_priv *priv;
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void __iomem *base;
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base = dev_request_mem_region(dev, 0);
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/* check hardware version */
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if (readl(base + XGMAC_VERSION) != 0x1012)
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return -EINVAL;
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priv = xzalloc(sizeof(*priv));
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priv->dev = dev;
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priv->base = base;
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priv->rxbuffer = dma_alloc_coherent(RX_BUF_SZ);
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priv->rx_chain = dma_alloc_coherent(RX_NUM_DESC * sizeof(struct xgmac_dma_desc));
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priv->tx_chain = dma_alloc_coherent(TX_NUM_DESC * sizeof(struct xgmac_dma_desc));
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edev = &priv->edev;
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edev->priv = priv;
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edev->open = xgmac_open;
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edev->send = xgmac_send;
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edev->recv = xgmac_recv;
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edev->halt = xgmac_halt;
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edev->get_ethaddr = xgmac_get_ethaddr;
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edev->set_ethaddr = xgmac_set_ethaddr;
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edev->parent = dev;
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eth_register(edev);
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return 0;
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}
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static __maybe_unused struct of_device_id xgmac_dt_ids[] = {
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{
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.compatible = "calxeda,hb-xgmac",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d hb_xgmac_driver = {
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.name = "hb-xgmac",
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.probe = hb_xgmac_probe,
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.of_compatible = DRV_OF_COMPAT(xgmac_dt_ids),
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};
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device_platform_driver(hb_xgmac_driver);
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