96 lines
3.2 KiB
C
96 lines
3.2 KiB
C
/*
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* Register definitions for the OMAP3 McSPI Controller
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*
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* Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
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*
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* Parts taken from linux/drivers/spi/omap2_mcspi.c
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* Copyright (C) 2005, 2006 Nokia Corporation
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*
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* Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _OMAP3_SPI_H_
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#define _OMAP3_SPI_H_
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#define OMAP3_MCSPI_MAX_FREQ 48000000
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/* OMAP3 McSPI registers */
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#define OMAP3_MCSPI REVISION 0x00
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#define OMAP3_MCSPI_SYSCONFIG 0x10
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#define OMAP3_MCSPI_SYSSTATUS 0x14
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#define OMAP3_MCSPI_IRQSTATUS 0x18
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#define OMAP3_MCSPI_IRQENABLE 0x1C
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#define OMAP3_MCSPI_WAKEUPENABLE 0x20
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#define OMAP3_MCSPI_SYST 0x24
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#define OMAP3_MCSPI_MODULCTRL 0x28
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#define OMAP3_MCSPI_CH_SIZE 0x14 /* bytes each */
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#define OMAP3_MCSPI_CHCONF0 0x2C /* also 0x40, 0x54, 0x68 */
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#define OMAP3_MCSPI_CHSTAT0 0x30 /* also 0x44, 0x58, 0x6C */
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#define OMAP3_MCSPI_CHCTRL0 0x34 /* also 0x48, 0x5C, 0x70 */
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#define OMAP3_MCSPI_TX0 0x38 /* also 0x4C, 0x60, 0x74 */
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#define OMAP3_MCSPI_RX0 0x3C /* also 0x50, 0x64, 0x78 */
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/* per-register bitmasks */
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#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
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#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
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#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
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#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
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#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
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#define OMAP3_MCSPI_MODULCTRL_SINGLE (1 << 0)
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#define OMAP3_MCSPI_MODULCTRL_MS (1 << 2)
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#define OMAP3_MCSPI_MODULCTRL_STEST (1 << 3)
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#define OMAP3_MCSPI_CHCONF_PHA (1 << 0)
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#define OMAP3_MCSPI_CHCONF_POL (1 << 1)
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#define OMAP3_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
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#define OMAP3_MCSPI_CHCONF_EPOL (1 << 6)
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#define OMAP3_MCSPI_CHCONF_WL_MASK (0x1f << 7)
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#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
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#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
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#define OMAP3_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
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#define OMAP3_MCSPI_CHCONF_DMAW (1 << 14)
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#define OMAP3_MCSPI_CHCONF_DMAR (1 << 15)
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#define OMAP3_MCSPI_CHCONF_DPE0 (1 << 16)
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#define OMAP3_MCSPI_CHCONF_DPE1 (1 << 17)
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#define OMAP3_MCSPI_CHCONF_IS (1 << 18)
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#define OMAP3_MCSPI_CHCONF_TURBO (1 << 19)
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#define OMAP3_MCSPI_CHCONF_FORCE (1 << 20)
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#define OMAP3_MCSPI_CHSTAT_RXS (1 << 0)
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#define OMAP3_MCSPI_CHSTAT_TXS (1 << 1)
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#define OMAP3_MCSPI_CHSTAT_EOT (1 << 2)
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#define OMAP3_MCSPI_CHCTRL_EN (1 << 0)
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#define OMAP3_MCSPI_WAKEUPENABLE_WKEN (1 << 0)
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struct omap3_spi_master {
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struct spi_master master;
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void __iomem *base; /* base of address space */
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void __iomem *regs; /* actual start of registers, omap4/am33xx have an
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* offset of 0x100 between start of register space
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* and registers
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*/
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int swap_miso_mosi;
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};
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#endif /* _OMAP3_SPI_H_ */
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