289 lines
9.2 KiB
C
289 lines
9.2 KiB
C
/*
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* Driver for AT91/AT32 LCD Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <io.h>
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#include <init.h>
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#include <linux/clk.h>
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#include <mach/hardware.h>
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#include <mach/atmel_hlcdc.h>
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#include <mach/io.h>
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#include <mach/cpu.h>
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#include <errno.h>
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#include <asm/mmu.h>
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#include "atmel_lcdfb.h"
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#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
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static void atmel_hlcdfb_stop(struct atmel_lcdfb_info *sinfo, u32 flags)
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{
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/* Disable DISP signal */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_DISPDIS);
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while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
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mdelay(1);
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/* Disable synchronization */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_SYNCDIS);
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while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
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mdelay(1);
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/* Disable pixel clock */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_CLKDIS);
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while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
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mdelay(1);
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/* Disable PWM */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDDIS, LCDC_LCDDIS_PWMDIS);
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while ((lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
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mdelay(1);
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if (!(flags & ATMEL_LCDC_STOP_NOWAIT))
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/* Wait for the end of DMA transfer */
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while (!(lcdc_readl(sinfo, ATMEL_LCDC_BASEISR) & LCDC_BASEISR_DMA))
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mdelay(10);
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/*FIXME: OVL DMA? */
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}
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static void atmel_hlcdfb_start(struct atmel_lcdfb_info *sinfo)
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{
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lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, LCDC_LCDEN_CLKEN);
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while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_CLKSTS))
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mdelay(1);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, LCDC_LCDEN_SYNCEN);
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while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_LCDSTS))
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mdelay(1);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, LCDC_LCDEN_DISPEN);
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while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_DISPSTS))
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mdelay(1);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDEN, LCDC_LCDEN_PWMEN);
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while (!(lcdc_readl(sinfo, ATMEL_LCDC_LCDSR) & LCDC_LCDSR_PWMSTS))
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mdelay(1);
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}
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struct atmel_hlcd_dma_desc {
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u32 address;
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u32 control;
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u32 next;
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};
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static void atmel_hlcdfb_update_dma(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->priv;
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unsigned long dma_addr;
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struct atmel_hlcd_dma_desc *desc;
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dma_addr = (u32)info->screen_base;
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dma_addr &= ~3UL;
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/* Setup the DMA descriptor, this descriptor will loop to itself */
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desc = sinfo->dma_desc;
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desc->address = dma_addr;
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/* Disable DMA transfer interrupt & descriptor loaded interrupt. */
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desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
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| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
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desc->next = (u32)desc;
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lcdc_writel(sinfo, ATMEL_LCDC_BASEADDR, desc->address);
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lcdc_writel(sinfo, ATMEL_LCDC_BASECTRL, desc->control);
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lcdc_writel(sinfo, ATMEL_LCDC_BASENEXT, desc->next);
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lcdc_writel(sinfo, ATMEL_LCDC_BASECHER, LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN);
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}
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static void atmel_hlcdfb_limit_screeninfo(struct fb_videomode *mode)
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{
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u32 hbpw, hfpw;
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if (cpu_is_at91sam9x5()) {
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hbpw = LCDC_LCDCFG3_HBPW;
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hfpw = LCDC_LCDCFG3_HFPW;
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} else {
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hbpw = LCDC2_LCDCFG3_HBPW;
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hfpw = LCDC2_LCDCFG3_HFPW;
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}
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/* Saturate vertical and horizontal timings at maximum values */
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mode->vsync_len = min_t(u32, mode->vsync_len,
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(LCDC_LCDCFG1_VSPW >> LCDC_LCDCFG1_VSPW_OFFSET) + 1);
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mode->upper_margin = min_t(u32, mode->upper_margin,
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(LCDC_LCDCFG2_VFPW >> LCDC_LCDCFG2_VFPW_OFFSET) + 1);
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mode->lower_margin = min_t(u32, mode->lower_margin,
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LCDC_LCDCFG2_VBPW >> LCDC_LCDCFG2_VBPW_OFFSET);
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mode->right_margin = min_t(u32, mode->right_margin,
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(hbpw >> LCDC_LCDCFG3_HBPW_OFFSET) + 1);
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mode->hsync_len = min_t(u32, mode->hsync_len,
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(LCDC_LCDCFG1_HSPW >> LCDC_LCDCFG1_HSPW_OFFSET) + 1);
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mode->left_margin = min_t(u32, mode->left_margin,
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(hfpw >> LCDC_LCDCFG3_HFPW_OFFSET) + 1);
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}
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static u32 atmel_hlcdfb_get_rgbmode(struct fb_info *info)
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{
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u32 value = 0;
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switch (info->bits_per_pixel) {
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case 1:
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value = LCDC_BASECFG1_CLUTMODE_1BPP | LCDC_BASECFG1_CLUTEN;
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break;
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case 2:
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value = LCDC_BASECFG1_CLUTMODE_2BPP | LCDC_BASECFG1_CLUTEN;
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break;
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case 4:
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value = LCDC_BASECFG1_CLUTMODE_4BPP | LCDC_BASECFG1_CLUTEN;
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break;
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case 8:
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value = LCDC_BASECFG1_CLUTMODE_8BPP | LCDC_BASECFG1_CLUTEN;
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break;
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case 12:
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value = LCDC_BASECFG1_RGBMODE_12BPP_RGB_444;
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break;
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case 16:
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if (info->transp.offset)
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value = LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444;
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else
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value = LCDC_BASECFG1_RGBMODE_16BPP_RGB_565;
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break;
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case 18:
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value = LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED;
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break;
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case 24:
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value = LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED;
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break;
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case 32:
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value = LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888;
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break;
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default:
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dev_err(&info->dev, "Cannot set video mode for %dbpp\n",
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info->bits_per_pixel);
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break;
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}
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return value;
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}
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static void atmel_hlcdfb_setup_core_base(struct fb_info *info)
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{
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struct atmel_lcdfb_info *sinfo = info->priv;
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struct atmel_lcdfb_platform_data *pdata = sinfo->pdata;
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struct fb_videomode *mode = info->mode;
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unsigned long value;
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unsigned long clk_value_khz;
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dev_dbg(&info->dev, "%s:\n", __func__);
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/* Set pixel clock */
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clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
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value = DIV_ROUND_CLOSEST(clk_value_khz, PICOS2KHZ(mode->pixclock));
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if (value < 1) {
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dev_notice(&info->dev, "using system clock as pixel clock\n");
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value = LCDC_LCDCFG0_CLKPWMSEL;
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} else {
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mode->pixclock = KHZ2PICOS(clk_value_khz / value);
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dev_dbg(&info->dev, " updated pixclk: %lu KHz\n",
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PICOS2KHZ(mode->pixclock));
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value = value - 2;
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dev_dbg(&info->dev, " * programming CLKDIV = 0x%08lx\n",
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value);
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value = (value << LCDC_LCDCFG0_CLKDIV_OFFSET);
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}
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value |= LCDC_LCDCFG0_CGDISBASE;
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG0, value);
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/* Initialize control register 5 */
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/* In 9x5, the default_lcdcon2 will use for LCDCFG5 */
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value = pdata->default_lcdcon2;
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value |= (sinfo->guard_time << LCDC_LCDCFG5_GUARDTIME_OFFSET)
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| LCDC_LCDCFG5_DISPDLY
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| LCDC_LCDCFG5_VSPDLYS;
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if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
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value |= LCDC_LCDCFG5_HSPOL;
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if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
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value |= LCDC_LCDCFG5_VSPOL;
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dev_dbg(&info->dev, " * LCDC_LCDCFG5 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG5, value);
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/* Vertical & Horizontal Timing */
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value = (mode->vsync_len - 1) << LCDC_LCDCFG1_VSPW_OFFSET;
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value |= (mode->hsync_len - 1) << LCDC_LCDCFG1_HSPW_OFFSET;
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dev_dbg(&info->dev, " * LCDC_LCDCFG1 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG1, value);
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value = (mode->upper_margin) << LCDC_LCDCFG2_VBPW_OFFSET;
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value |= (mode->lower_margin - 1) << LCDC_LCDCFG2_VFPW_OFFSET;
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dev_dbg(&info->dev, " * LCDC_LCDCFG2 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG2, value);
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value = (mode->left_margin - 1) << LCDC_LCDCFG3_HBPW_OFFSET;
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value |= (mode->right_margin - 1) << LCDC_LCDCFG3_HFPW_OFFSET;
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dev_dbg(&info->dev, " * LCDC_LCDCFG3 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG3, value);
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/* Display size */
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value = (mode->yres - 1) << LCDC_LCDCFG4_RPF_OFFSET;
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value |= (mode->xres - 1) << LCDC_LCDCFG4_PPL_OFFSET;
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dev_dbg(&info->dev, " * LCDC_LCDCFG4 = %08lx\n", value);
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG4, value);
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lcdc_writel(sinfo, ATMEL_LCDC_BASECFG0, LCDC_BASECFG0_BLEN_AHB_INCR16 | LCDC_BASECFG0_DLBO);
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lcdc_writel(sinfo, ATMEL_LCDC_BASECFG1, atmel_hlcdfb_get_rgbmode(info));
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lcdc_writel(sinfo, ATMEL_LCDC_BASECFG2, 0);
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lcdc_writel(sinfo, ATMEL_LCDC_BASECFG3, 0); /* Default color */
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lcdc_writel(sinfo, ATMEL_LCDC_BASECFG4, LCDC_BASECFG4_DMA);
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/* Disable all interrupts */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDIDR, ~0UL);
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lcdc_writel(sinfo, ATMEL_LCDC_BASEIDR, ~0UL);
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/* Enable BASE LAYER overflow interrupts, if want to enable DMA interrupt, also need set it at LCDC_BASECTRL reg */
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lcdc_writel(sinfo, ATMEL_LCDC_BASEIER, LCDC_BASEIER_OVR);
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/* FIXME: Let video-driver register a callback */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDIER, LCDC_LCDIER_FIFOERRIE |
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LCDC_LCDIER_BASEIE | LCDC_LCDIER_HEOIE);
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}
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static void atmel_hlcdfb_init_contrast(struct atmel_lcdfb_info *sinfo)
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{
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/* have some default contrast/backlight settings */
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lcdc_writel(sinfo, ATMEL_LCDC_LCDCFG6, LCDC_LCDCFG6_PWMPOL |
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(ATMEL_LCDC_CVAL_DEFAULT << LCDC_LCDCFG6_PWMCVAL_OFFSET));
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}
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struct atmel_lcdfb_devdata atmel_hlcdfb_data = {
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.start = atmel_hlcdfb_start,
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.stop = atmel_hlcdfb_stop,
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.update_dma = atmel_hlcdfb_update_dma,
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.setup_core = atmel_hlcdfb_setup_core_base,
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.init_contrast = atmel_hlcdfb_init_contrast,
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.limit_screeninfo = atmel_hlcdfb_limit_screeninfo,
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.dma_desc_size = sizeof(struct atmel_hlcd_dma_desc),
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};
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static int atmel_hlcdc_probe(struct device_d *dev)
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{
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return atmel_lcdc_register(dev, &atmel_hlcdfb_data);
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}
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static struct driver_d atmel_hlcdc_driver = {
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.name = "atmel_hlcdfb",
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.probe = atmel_hlcdc_probe,
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};
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device_platform_driver(atmel_hlcdc_driver);
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