188 lines
7.3 KiB
C
188 lines
7.3 KiB
C
/*
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* TI Omap4 Frame Buffer device driver
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*
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* Copyright (C) 2013 Christoph Fritz <chf.fritz@googlemail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
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#define H_BAREBOX_DRIVER_VIDEO_OMAP4_REGS_H
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#include <types.h>
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#include <common.h>
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#define OFB_TIMEOUT (128 * USECOND)
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#define _ofb_read(io, reg) __raw_readl((io)+(reg))
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#define _ofb_write(val, io, reg) __raw_writel((val), (io)+(reg))
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/* TRM: 10.1.3.2 DSS Registers */
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#define O4_DSS_REVISION 0x0
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#define O4_DSS_SYSSTATUS 0x14
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#define O4_DSS_CTRL 0x40
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#define O4_DSS_STATUS 0x5c
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#define o4_dss_read(reg) _ofb_read(fbi->dss, reg)
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#define o4_dss_write(val, reg) _ofb_write(val, fbi->dss, reg)
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/* TRM: 10.2.7.3 Display Controller Registers */
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#define O4_DISPC_REVISION 0x0
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#define O4_DISPC_IRQSTATUS 0x18
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#define O4_DISPC_VID1_BA0 0xbc
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#define O4_DISPC_VID1_BA1 0xc0
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#define O4_DISPC_VID1_POSITION 0xc4
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#define O4_DISPC_VID1_SIZE 0xc8
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#define O4_DISPC_VID1_ATTRIBUTES 0xcc
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#define O4_DISPC_VID1_ROW_INC 0xd8
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#define O4_DISPC_VID1_PIXEL_INC 0xdc
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#define O4_DISPC_VID1_PICTURE_SIZE 0xe4
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#define O4_DISPC_VID1_PRELOAD 0x230
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#define O4_DISPC_CONTROL2 0x238
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#define O4_DISPC_DEFAULT_COLOR2 0x3ac
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#define O4_DISPC_SIZE_LCD2 0x3cc
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#define O4_DISPC_TIMING_H2 0x400
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#define O4_DISPC_TIMING_V2 0x404
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#define O4_DISPC_POL_FREQ2 0x408
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#define O4_DISPC_DIVISOR2 0x40c
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#define O4_DISPC_DIVISOR 0x804
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#define o4_dispc_read(reg) _ofb_read(fbi->dispc, reg)
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#define o4_dispc_write(val, reg) _ofb_write(val, fbi->dispc, reg)
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#define DSS_DISPC_VIDn_POSITION_VIDPOSX(_x) ((_x) << 0)
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#define DSS_DISPC_VIDn_POSITION_VIDPOSY(_y) ((_y) << 16)
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#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEX(_x) ((_x) << 0)
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#define DSS_DISPC_VIDn_PICTURE_SIZE_VIDORGSIZEY(_y) ((_y) << 16)
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#define DSS_DISPC_VIDn_SIZE_VIDSIZEX(_x) ((_x) << 0)
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#define DSS_DISPC_VIDn_SIZE_VIDSIZEY(_y) ((_y) << 16)
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#define DSS_DISPC_SIZE_LCD_PPL(_x) ((_x) << 0)
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#define DSS_DISPC_SIZE_LCD_LPP(_y) ((_y) << 16)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDENABLE (1u << 0)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(_fmt) ((_fmt) << 1)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB12 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(4u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(5u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB16 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(6u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB16o \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(7u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB24u \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(8u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGB24p \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(9u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_YUV2 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(10u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_UYVY \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(11u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_ARGB32 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(12u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_RGBA32 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(13u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT_xRGB32 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDFORMAT(14u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(_b) ((_b) << 14)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_2x128 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(0u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_4x128 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(1u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE_8x128 \
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DSS_DISPC_VIDn_ATTRIBUTES_VIDBURSTSIZE(2u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDCHANNELOUT (1u << 16)
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#define DSS_DISPC_VIDn_ATTRIBUTES_SELFREFRESHAUTO (1u << 17)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDFIFOPRELOAD (1u << 19)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDVERTICALTAPS (1u << 21)
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#define DSS_DISPC_VIDn_ATTRIBUTES_DOUBLESTRIDE (1u << 22)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDARBITRATION (1u << 23)
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#define DSS_DISPC_VIDn_ATTRIBUTES_VIDSELFREFRESH (1u << 24)
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#define DSS_DISPC_VIDn_ATTRIBUTES_ZORDERENABLE (1u << 25)
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#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(_b) ((_b) << 30)
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#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_PRIMARY_LCD \
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DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(0u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_SECONDARY_LCD \
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DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(1u)
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#define DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2_WRITEBACK_MEM \
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DSS_DISPC_VIDn_ATTRIBUTES_CHANNELOUT2(3u)
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#define DSS_DISPC_CONTROL_LCDENABLE (1u << 0)
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#define DSS_DISPC_CONTROL_TVENABLE (1u << 1)
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#define DSS_DISPC_CONTROL_MONOCOLOR (1u << 2)
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#define DSS_DISPC_CONTROL_STNTFT (1u << 3)
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#define DSS_DISPC_CONTROL_M8B (1u << 4)
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#define DSS_DISPC_CONTROL_GOLCD (1u << 5)
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#define DSS_DISPC_CONTROL_GOTV (1u << 6)
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#define DSS_DISPC_CONTROL_STDITHERENABLE (1u << 7)
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#define DSS_DISPC_CONTROL_TFTDATALINES(_l) ((_l) << 8)
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#define DSS_DISPC_CONTROL_TFTDATALINES_12 \
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DSS_DISPC_CONTROL_TFTDATALINES(0u)
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#define DSS_DISPC_CONTROL_TFTDATALINES_16 \
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DSS_DISPC_CONTROL_TFTDATALINES(1u)
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#define DSS_DISPC_CONTROL_TFTDATALINES_18 \
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DSS_DISPC_CONTROL_TFTDATALINES(2u)
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#define DSS_DISPC_CONTROL_TFTDATALINES_24 \
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DSS_DISPC_CONTROL_TFTDATALINES(3u)
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#define DSS_DISPC_CONTROL_STALLMODE (1u << 11)
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#define DSS_DISPC_CONTROL_OVERLAYOPTIMIZATION (1u << 12)
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#define DSS_DISPC_CONTROL_GPIN0 (1u << 13) /* ro */
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#define DSS_DISPC_CONTROL_GPIN1 (1u << 14) /* ro */
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#define DSS_DISPC_CONTROL_GPOUT0 (1u << 15)
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#define DSS_DISPC_CONTROL_GPOUT1 (1u << 16)
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#define DSS_DISPC_CONTROL_HT(_ht) ((_ht) << 17)
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#define DSS_DISPC_CONTROL_TDMENABLE (1u << 20)
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#define DSS_DISPC_CONTROL_TDMPARALLELMODE(_pm) ((_pm) << 21)
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#define DSS_DISPC_CONTROL_TDMCYCLEFORMAT(_cf) ((_cf) << 23)
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#define DSS_DISPC_CONTROL_TDMUNUSEDBITS(_ub) ((_ub) << 25)
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#define DSS_DISPC_CONTROL_PCKFREEENABLE (1u << 27)
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#define DSS_DISPC_CONTROL_LCDENABLESIGNAL (1u << 28)
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#define DSS_DISPC_CONTROL_LCDENABLEPOL (1u << 29)
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#define DSS_DISPC_CONTROL_SPATIALTEMPD(_df) ((_df) << 30)
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#define DSS_DISPC_POL_FREQ_IVS (1u << 12)
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#define DSS_DISPC_POL_FREQ_IHS (1u << 13)
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#define DSS_DISPC_POL_FREQ_IPC (1u << 14)
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#define DSS_DISPC_POL_FREQ_IEO (1u << 15)
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#define DSS_DISPC_POL_FREQ_RF (1u << 16)
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#define DSS_DISPC_POL_FREQ_ONOFF (1u << 17)
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#define DSS_DISPC_TIMING_H_HSW(_hsw) ((_hsw) << 0)
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#define DSS_DISPC_TIMING_H_HFP(_hfp) ((_hfp) << 8)
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#define DSS_DISPC_TIMING_H_HBP(_hbp) ((_hbp) << 20)
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#define DSS_DISPC_TIMING_V_VSW(_vsw) ((_vsw) << 0)
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#define DSS_DISPC_TIMING_V_VFP(_vfp) ((_vfp) << 8)
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#define DSS_DISPC_TIMING_V_VBP(_vbp) ((_vbp) << 20)
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#define DSS_DISPC_DIVISOR_ENABLE (1u << 0)
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#define DSS_DISPC_DIVISOR_LCD(_lcd) ((_lcd) << 16)
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#define DSS_DISPC_DIVISOR2_PCD(_pcd) ((_pcd) << 0)
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#define DSS_DISPC_DIVISOR2_LCD(_lcd) ((_lcd) << 16)
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#define DSS_DISPC_IRQSTATUS_FRAMEDONE (1u << 0)
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#define DSS_DISPC_IRQSTATUS_FRAMEDONE2 (1u << 22)
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#define DSS_DSS_SYSSTATUS_RESETDONE (1u << 0)
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#endif /* H_BAREBOX_DRIVER_VIDEO_O4_REGS_H */
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