227 lines
7.2 KiB
C
227 lines
7.2 KiB
C
/*
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* (c) 2012 Juergen Beisert <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Note: this driver works for the i.MX28 SoC. It might work for the
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* i.MX23 Soc as well, but is not tested yet.
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <errno.h>
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#include <malloc.h>
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#include <watchdog.h>
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#include <reset_source.h>
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#define MXS_RTC_CTRL 0x0
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#define MXS_RTC_SET_ADDR 0x4
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#define MXS_RTC_CLR_ADDR 0x8
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# define MXS_RTC_CTRL_WATCHDOGEN (1 << 4)
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#define MXS_RTC_STAT 0x10
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# define MXS_RTC_STAT_WD_PRESENT (1 << 29)
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#define MXS_RTC_WATCHDOG 0x50
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/* HW_RTC_PERSISTENT0 - holds bits used to configure various hardware settings */
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#define MXS_RTC_PERSISTENT0 0x60
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/* FIXME */
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# define MXS_RTC_PERSISTENT0_SPARE_ANALOG (1 << 22)
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/* dubious meaning from inside the SoC's firmware ROM */
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# define MXS_RTC_PERSISTENT0_EXT_RST (1 << 21)
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/* dubious meaning from inside the SoC's firmware ROM */
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# define MXS_RTC_PERSISTENT0_THM_RST (1 << 20)
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/* reserved on i.MX28 */
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# define MXS_RTC_PERSISTENT0_RELEASE_GND (1 << 19)
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# define MXS_RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18)
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# define MXS_RTC_PERSISTENT0_AUTO_RESTART (1 << 17)
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# define MXS_RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16)
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# define MXS_RTC_PERSISTENT0_LOWERBIAS (1 << 14)
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# define MXS_RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13)
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# define MXS_RTC_PERSISTENT0_MSEC_RES (1 << 8)
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# define MXS_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
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# define MXS_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
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# define MXS_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
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# define MXS_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
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# define MXS_RTC_PERSISTENT0_LCK_SECS (1 << 3)
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# define MXS_RTC_PERSISTENT0_ALARM_EN (1 << 2)
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# define MXS_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
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# define MXS_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
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/* HW_RTC_PERSISTENT1 - holds bits related to the ROM and redundant boot handling */
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#define MXS_RTC_PERSISTENT1 0x70
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/*
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* some of the following bits are for error reporting from ROM to the chained
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* firmware. It seems, if the error reporting bits are not cleared when the
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* chained firmware is running, the next time the following rule is active:
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* "Loader enters recovery mode if any non-USB boot mode has an error.
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* Which results into a system that seems not to start anymore.
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*/
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/* dubious meaning from inside the SoC's firmware ROM */
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# define MXS_RTC_PERSISTENT1_FORCE_UPDATER (1 << 31)
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/* names are from the i.MX28 datasheet. Undocumented behaviour */
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# define MXS_RTC_PERSISTENT1_ENUMERATE_500MA_TWICE (1 << 12)
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# define MXS_RTC_PERSISTENT1_USB_BOOT_PLAYER_MODE (1 << 11)
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# define MXS_RTC_PERSISTENT1_SKIP_CHECKDISK (1 << 10)
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# define MXS_RTC_PERSISTENT1_USB_LOW_POWER_MODE (1 << 9)
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# define MXS_RTC_PERSISTENT1_OTG_HNP_BIT (1 << 8)
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# define MXS_RTC_PERSISTENT1_OTG_ATL_ROLE_BIT (1 << 7)
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/*
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* a few undocumented bits
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*/
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# define MXS_RTC_PERSISTENT1_SD_INIT_SEQ_2_ENABLE (1 << 6)
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# define MXS_RTC_PERSISTENT1_SD_CMD0_DISABLE (1 << 5)
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# define MXS_RTC_PERSISTENT1_SD_INIT_SEQ_1_DISABLE (1 << 4)
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/*
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* If this bit is set, ROM puts the SD/MMC card in high-speed mode.
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* If this bit is set, the ROM driver will use a maximum speed based on the
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* results of device identification and limited by choices available in the
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* SSP clock index.
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*/
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# define MXS_RTC_PERSISTENT1_SD_SPEED_ENABLE (1 << 3)
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/*
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* The NAND driver sets this bit to indicate to the SDK that the boot image
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* has ECC errors that reached the warning threshold. The SDK regenerates the
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* firmware by copying it from the backup image. The SDK clears this bit.
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* This bit had change its meaning from i.XM23 to i.MX28. Refer section
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* 35.8 "NAND Boot Mode" for further details in the i.MX23 RM.
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*/
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# define MXS_RTC_PERSISTENT1_NAND_SDK_BLOCK_REWRITE (1 << 2)
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/*
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* When this bit is set, ROM attempts to boot from the secondary image if the
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* boot driver supports it. This bit is set by the ROM boot driver and cleared
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* by the SDK after repair.
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* If not reset, the ROM seems to continue to start from the secondary image
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* which will fail forever if there is no secondary image
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*/
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# define MXS_RTC_PERSISTENT1_NAND_SECONDARY_BOOT (1 << 1)
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/*
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* When this bit is set, the ROM code forces the system to boot in recovery
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* mode, regardless of the selected mode. The ROM clears the bit.
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*/
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# define MXS_RTC_PERSISTENT1_FORCE_RECOVERY (1 << 0)
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#define MXS_RTC_DEBUG 0xc0
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#define WDOG_TICK_RATE 1000 /* the watchdog uses a 1 kHz clock rate */
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struct imx28_wd {
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struct watchdog wd;
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void __iomem *regs;
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};
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#define to_imx28_wd(h) container_of(h, struct imx28_wd, wd)
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static int imx28_watchdog_set_timeout(struct watchdog *wd, unsigned timeout)
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{
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struct imx28_wd *pwd = (struct imx28_wd *)to_imx28_wd(wd);
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void __iomem *base;
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if (timeout > (ULONG_MAX / WDOG_TICK_RATE))
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return -EINVAL;
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if (timeout) {
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writel(timeout * WDOG_TICK_RATE, pwd->regs + MXS_RTC_WATCHDOG);
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base = pwd->regs + MXS_RTC_SET_ADDR;
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} else {
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base = pwd->regs + MXS_RTC_CLR_ADDR;
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}
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writel(MXS_RTC_CTRL_WATCHDOGEN, base + MXS_RTC_CTRL);
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writel(MXS_RTC_PERSISTENT1_FORCE_UPDATER, base + MXS_RTC_PERSISTENT1);
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return 0;
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}
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static void __maybe_unused imx28_detect_reset_source(const struct imx28_wd *p)
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{
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u32 reg;
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reg = readl(p->regs + MXS_RTC_PERSISTENT0);
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if (reg & MXS_RTC_PERSISTENT0_EXT_RST) {
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writel(MXS_RTC_PERSISTENT0_EXT_RST,
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p->regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
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/*
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* if the RTC has woken up the SoC, additionally the ALARM_WAKE
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* bit is set. This bit should have precedence, because it
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* reports the real event, why we are here.
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*/
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if (reg & MXS_RTC_PERSISTENT0_ALARM_WAKE) {
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writel(MXS_RTC_PERSISTENT0_ALARM_WAKE,
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p->regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
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reset_source_set(RESET_WKE);
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return;
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}
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reset_source_set(RESET_POR);
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return;
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}
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if (reg & MXS_RTC_PERSISTENT0_THM_RST) {
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writel(MXS_RTC_PERSISTENT0_THM_RST,
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p->regs + MXS_RTC_PERSISTENT0 + MXS_RTC_CLR_ADDR);
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reset_source_set(RESET_RST);
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return;
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}
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reset_source_set(RESET_RST);
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}
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static int imx28_wd_probe(struct device_d *dev)
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{
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struct imx28_wd *priv;
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int rc;
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priv = xzalloc(sizeof(struct imx28_wd));
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priv->regs = dev_request_mem_region(dev, 0);
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priv->wd.set_timeout = imx28_watchdog_set_timeout;
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if (!(readl(priv->regs + MXS_RTC_STAT) & MXS_RTC_STAT_WD_PRESENT)) {
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rc = -ENODEV;
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goto on_error;
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}
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/* disable the debug feature to ensure a working WD */
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writel(0x00000000, priv->regs + MXS_RTC_DEBUG);
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rc = watchdog_register(&priv->wd);
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if (rc != 0)
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goto on_error;
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if (IS_ENABLED(CONFIG_RESET_SOURCE))
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imx28_detect_reset_source(priv);
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dev->priv = priv;
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return 0;
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on_error:
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free(priv);
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return rc;
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}
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static void imx28_wd_remove(struct device_d *dev)
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{
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struct imx28_wd *priv= dev->priv;
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watchdog_deregister(&priv->wd);
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free(priv);
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}
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static struct driver_d imx28_wd_driver = {
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.name = "im28wd",
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.probe = imx28_wd_probe,
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.remove = imx28_wd_remove,
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};
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device_platform_driver(imx28_wd_driver);
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