95 lines
3.1 KiB
ReStructuredText
95 lines
3.1 KiB
ReStructuredText
Altera SoCFPGA
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==============
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Alteras SoCFPGA SoCs have a two-stage boot process. The first stage is
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known as preloader which loads the second stage bootloader. barebox can act
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as both the first and the second stage loader.
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In barebox the preloader is called xload, so to build as a first stage loader,
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build the ``socfpga-xload_defconfig``; for second stage use the normal
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``socfpga_defconfig``.
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Bootstrapping
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-------------
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The supported bootsource is a SD card. The Boot ROM searches for a partition of
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type A2 and loads what it finds there. When barebox is placed in such a partition
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it will then itself try and mount the second partition of the SD card, which must
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be of type FAT32. On this partition barebox searches for a file called barebox.bin.
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To boot barebox on a Terasic SoCkit, the procedure is as follows (sdb1 is the A2 and
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sdb2 the FAT32 partition)::
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mount -t fat /dev/sdb2 /mnt
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make socfpga-xload_defconfig
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make
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make socfpga_defconfig
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make
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barebox has now generated multiple files in the images directory. So for the SoCkit
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proceed with::
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cat images/barebox-socfpga-sockit-xload.img > /dev/sdb1
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cp images/barebox-socfpga-sockit.img /mnt/barebox.bin
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umount /mnt
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For the EBV Socrates use ``images/barebox-socfpga-socrates(-xload).img`` instead.
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Updating handoff files
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----------------------
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(Tools needed: Quartus II + SoCEDS)
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As barebox uses some of the autogenerated files from Quartus II, every
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time Altera makes a new release, there might be some updates to the
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handoff files. As these files are split up in the code base and generated
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explicitely for some specific U-boot code base, some manual work might be
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necessary.
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The boardspecific files for `arch/arm/boards/<yourboard>` are:
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* iocsr_config_cyclone5.c
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* pinmux_config_cyclone5.c -> pinmux_config.c
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* pll_config.h
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* sdram/sdram_config.h -> sdram_config.h
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* sequencer_auto.h
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* sequencer_auto_ac_init.c
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* sequencer_auto_inst_init.c
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* sequencer_defines.h
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To update the handoff files, the following procedure is necessary::
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1. Regenerate the project with Qsys
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2. Load up your project in Quartus II and assemble the design
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3. Go to the SoCEDS installation and run
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``./embedded_command_shell.sh``
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4. Now run ``bsp-editor``
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5. Create a new BSP
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6. Select the directory `hps_isw_handoff/soc_system_hps_0` under the
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preloader settings directory
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7. Click ``Ok`` than ``Generate``
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Now run the command::
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scripts/socfpga_import_preloader <SPL_GENERATED_DIR> <ISW_HANDOFF> <BOARD_DIRECTORY>
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where `<SPL_GENERATED_DIR>` is the directory where the bsp-editor generated the files,
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`<ISW_HANDOFF>` is the directory where Quartus generated the handoff files, and
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`<BOARD_DIRECTORY>` is your board directory under `arch/arm/boards`.
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The following files are generic and belong into the
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`arch/arm/mach-socfpga` directory tree:
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* sdram_io.h
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* sequencer.c
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* sequencer.h
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* sequencer_defines.h
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* system.h
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* tclrpt.h
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To add these files, run::
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scripts/socfpga_get_sequencer <UBOOT-SRC> scripts/socfpga_sequencer_defines_defaults
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where `<UBOOT-SRC>` is the directory where the Altera bsp-editor generated the u-boot
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directory. Refer to the Altera documentation for how to use the bsp-editor.
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