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barebox/arch/ppc/cpu-85xx
Renaud Barbier 7e1e8aac7b ppc: 85xx: CCSRBAR mapping moved to start-up code.
Move the configuration, control and status register base address
(CCSRBAR) relocation to the start-up processing. This addresses
TLB faults found during testing  on the Freescale P1010RDB and
also matches the current U-Boot functionality.

Signed-off-by: Renaud Barbier <renaud.barbier@ge.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2014-07-28 07:26:27 +02:00
..
Makefile ppc: add support for memtest with cache disabled 2014-03-03 09:07:20 +01:00
fixed_ivor.S Treewide: remove address of the Free Software Foundation 2012-09-17 10:57:41 +02:00
mmu.c ppc: add support for memtest with cache disabled 2014-03-03 09:07:20 +01:00
resetvec.S Initial e500v2 start up code 2012-05-17 20:33:38 +02:00
start.S ppc: 85xx: CCSRBAR mapping moved to start-up code. 2014-07-28 07:26:27 +02:00
tlb.c ppc: add support for memtest with cache disabled 2014-03-03 09:07:20 +01:00
traps.c Treewide: remove address of the Free Software Foundation 2012-09-17 10:57:41 +02:00