234 lines
6.5 KiB
C
234 lines
6.5 KiB
C
/*
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* Copyright (C) 2015 Jan Luebbe <jluebbe@lasnet.de>
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*
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* This file is part of barebox.
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* See file CREDITS for list of people who contributed to this project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <globalvar.h>
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#include <gpio.h>
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#include <envfs.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <libfile.h>
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#include <net.h>
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#include <linux/sizes.h>
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#include <linux/clk.h>
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#include <asm/armlinux.h>
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#define PINMUX0 0x01c40000
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#define PINMUX1 0x01c40004
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#define PINMUX1_I2C BIT(7)
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#define VDD3P3V_PWDN (0x01c40048)
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#include <platform_data/eth-davinci-emac.h>
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#define EMAC_BASE_ADDR 0x01C80000
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#define EMAC_WRAPPER_BASE_ADDR 0x01C81000
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#define EMAC_WRAPPER_RAM_ADDR 0x01C82000
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#define EMAC_MDIO_BASE_ADDR 0x01C84000
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static struct resource dm644x_emac_resources[] = {
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{
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.start = EMAC_BASE_ADDR,
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.end = EMAC_BASE_ADDR + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = EMAC_WRAPPER_BASE_ADDR,
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.end = EMAC_WRAPPER_BASE_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = EMAC_MDIO_BASE_ADDR,
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.end = EMAC_MDIO_BASE_ADDR + 0xff,
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.flags = IORESOURCE_MEM,
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}, {
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.start = EMAC_WRAPPER_RAM_ADDR,
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.end = EMAC_WRAPPER_RAM_ADDR + 0x1fff, /* 8kB */
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.flags = IORESOURCE_MEM,
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}
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};
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static struct davinci_emac_platform_data dm644x_emac_pdata = {
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.force_link = false,
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.interface_rmii = false,
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.phy_addr = 1,
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};
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static struct device_d dm644x_emac_device = {
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.id = DEVICE_ID_DYNAMIC,
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.name = "davinci_emac",
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.num_resources = ARRAY_SIZE(dm644x_emac_resources),
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.resource = dm644x_emac_resources,
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.platform_data = &dm644x_emac_pdata,
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};
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static void sysmobts_config_eeprom(const char *compatible)
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{
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struct device_node *node;
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node = of_find_node_by_path("/i2c/eeprom@50");
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if (!node) {
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pr_err("can't find eeprom node to configure\n");
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return;
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}
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of_set_property(node, "compatible", compatible, strlen(compatible) + 1,
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1);
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of_device_enable(node);
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}
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static void sysmobts_board_detect(void)
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{
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int board_ver, board_cfg;
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char variant[4];
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board_ver = gpio_get_value(15);
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board_ver |= gpio_get_value(16) << 1;
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board_ver |= gpio_get_value(17) << 2;
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board_cfg = gpio_get_value(10);
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board_cfg |= gpio_get_value(11) << 1;
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board_cfg |= gpio_get_value(12) << 3;
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board_cfg |= gpio_get_value(13) << 4;
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board_cfg |= gpio_get_value(14) << 5;
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variant[0] = 'A' + board_ver;
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variant[1] = '.';
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variant[2] = '0' + board_cfg;
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variant[3] = '\0';
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globalvar_add_simple("board.variant", variant);
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printf("detected 'sysmobts_v2 %s'\n", variant);
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/* enable the correct eeprom */
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if (board_ver <= 2) {
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sysmobts_config_eeprom("24c02");
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} else {
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sysmobts_config_eeprom("24c64");
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}
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/* disable nand write protect */
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if (board_ver >= 5) {
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gpio_direction_output(33, 1);
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udelay(100);
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}
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}
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static int sysmobts_set_ethaddr(void)
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{
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char addr[6];
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int fd, ret;
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fd = open("/dev/eeprom0", O_RDONLY);
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if (fd < 0) {
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ret = fd;
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goto err;
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}
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ret = read_full(fd, addr, 6);
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if (ret < 0)
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goto err_open;
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eth_register_ethaddr(0, addr);
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ret = 0;
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err_open:
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close(fd);
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err:
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if (ret)
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pr_err("can't read eeprom /dev/eeprom0 (%s)\n", strerror(ret));
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return ret;
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}
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#define MACH_TYPE_SYSMOBTS_V2 3758
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static void sysmobts_devices_shutdown(void)
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{
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writel(readl(PINMUX1) | PINMUX1_I2C, PINMUX1);
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}
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postdevshutdown_exitcall(sysmobts_devices_shutdown);
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static int sysmobts_coredevices_init(void)
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{
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writel(0, VDD3P3V_PWDN);
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writel(0x8000000f, PINMUX0);
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writel(0x00050187, PINMUX1);
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writel(readl(PINMUX1) & ~PINMUX1_I2C, PINMUX1);
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sysmobts_board_detect();
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return 0;
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}
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coredevice_initcall(sysmobts_coredevices_init);
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#define DAVINCI_PLLM (0x01C40910) /* PLL 1 Multiplier */
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#define DAVINCI_AWCCR (0x01E00004) /* EMIF-A async wait cycle config register. */
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#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
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#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
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#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
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#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
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static int sysmobts_devices_init(void)
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{
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struct clk *dsp_clk;
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int ret;
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/* Configure AEMIF AWCCR */
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writel(DAVINCI_AWCCR_VAL, DAVINCI_AWCCR);
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/* DM644X @ 594/297 MHz */
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if ( (readl(DAVINCI_PLLM) & 0x0FF) < 22 ) {
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/* Configure AEMIF CS3 (fpga) */
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writel(DAVINCI_A2CR_VAL, DAVINCI_A2CR);
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/* DM644X @ 810/405 MHz */
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} else {
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/* Configure AEMIF CS3 (fpga) */
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writel(DAVINCI_A2CR_VAL8, DAVINCI_A2CR);
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}
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sysmobts_set_ethaddr();
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platform_device_register(&dm644x_emac_device);
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defaultenv_append_directory(defaultenv_sysmobts);
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armlinux_set_architecture(MACH_TYPE_SYSMOBTS_V2);
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dsp_clk = clk_get(NULL, "dsp");
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if (IS_ERR(dsp_clk)) {
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ret = PTR_ERR(dsp_clk);
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pr_err("unable to get DSP clock, err %d\n", ret);
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return 1;
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}
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ret = clk_enable(dsp_clk);
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if (ret < 0) {
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pr_err("unable to enable DSP clock, err %d\n", ret);
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return 1;
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}
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return 0;
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}
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device_initcall(sysmobts_devices_init);
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