379 lines
8.3 KiB
C
379 lines
8.3 KiB
C
/*
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* TI DaVinci DM644x chip specific setup
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <common.h>
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#include <init.h>
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#include <linux/clk.h>
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#include <mach/common.h>
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#include <mach/psc.h>
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#include "clock.h"
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#define DM644X_REF_FREQ 27000000
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#define DM644X_EMAC_BASE 0x01c80000
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#define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
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#define DM644X_EMAC_CNTRL_OFFSET 0x0000
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#define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
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#define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
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#define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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};
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static struct pll_data pll2_data = {
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.num = 2,
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.phys_base = DAVINCI_PLL2_BASE,
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};
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static struct clk ref_clk = {
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.name = "ref_clk",
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.rate = DM644X_REF_FREQ,
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};
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static struct clk pll1_clk = {
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.name = "pll1",
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.parent = &ref_clk,
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.pll_data = &pll1_data,
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.flags = CLK_PLL,
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};
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static struct clk pll1_sysclk1 = {
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.name = "pll1_sysclk1",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll1_sysclk2 = {
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.name = "pll1_sysclk2",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll1_sysclk3 = {
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.name = "pll1_sysclk3",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV3,
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};
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static struct clk pll1_sysclk5 = {
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.name = "pll1_sysclk5",
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.parent = &pll1_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV5,
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};
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static struct clk pll1_aux_clk = {
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.name = "pll1_aux_clk",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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};
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static struct clk pll1_sysclkbp = {
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.name = "pll1_sysclkbp",
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.parent = &pll1_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk pll2_clk = {
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.name = "pll2",
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.parent = &ref_clk,
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.pll_data = &pll2_data,
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.flags = CLK_PLL,
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};
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static struct clk pll2_sysclk1 = {
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.name = "pll2_sysclk1",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV1,
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};
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static struct clk pll2_sysclk2 = {
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.name = "pll2_sysclk2",
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.parent = &pll2_clk,
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.flags = CLK_PLL,
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.div_reg = PLLDIV2,
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};
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static struct clk pll2_sysclkbp = {
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.name = "pll2_sysclkbp",
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.parent = &pll2_clk,
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.flags = CLK_PLL | PRE_PLL,
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.div_reg = BPDIV
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};
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static struct clk dsp_clk = {
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.name = "dsp",
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.parent = &pll1_sysclk1,
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.lpsc = DAVINCI_LPSC_GEM,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.usecount = 1, /* REVISIT how to disable? */
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};
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static struct clk arm_clk = {
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.name = "arm",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_ARM,
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.flags = ALWAYS_ENABLED,
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};
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static struct clk vicp_clk = {
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.name = "vicp",
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.parent = &pll1_sysclk2,
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.lpsc = DAVINCI_LPSC_IMCOP,
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.domain = DAVINCI_GPSC_DSPDOMAIN,
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.usecount = 1, /* REVISIT how to disable? */
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};
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static struct clk vpss_master_clk = {
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.name = "vpss_master",
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.parent = &pll1_sysclk3,
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.lpsc = DAVINCI_LPSC_VPSSMSTR,
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.flags = CLK_PSC,
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};
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static struct clk vpss_slave_clk = {
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.name = "vpss_slave",
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.parent = &pll1_sysclk3,
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.lpsc = DAVINCI_LPSC_VPSSSLV,
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};
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static struct clk uart0_clk = {
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.name = "uart0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART0,
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};
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static struct clk uart1_clk = {
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.name = "uart1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART1,
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};
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static struct clk uart2_clk = {
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.name = "uart2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_UART2,
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};
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static struct clk emac_clk = {
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.name = "emac",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
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};
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static struct clk i2c_clk = {
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.name = "i2c",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_I2C,
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};
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static struct clk ide_clk = {
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.name = "ide",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_ATA,
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};
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static struct clk asp_clk = {
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.name = "asp0",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_McBSP,
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};
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static struct clk mmcsd_clk = {
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.name = "mmcsd",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_MMC_SD,
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};
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static struct clk spi_clk = {
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.name = "spi",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_SPI,
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};
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static struct clk gpio_clk = {
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.name = "gpio",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_GPIO,
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};
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static struct clk usb_clk = {
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.name = "usb",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_USB,
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};
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static struct clk vlynq_clk = {
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.name = "vlynq",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_VLYNQ,
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};
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static struct clk aemif_clk = {
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.name = "aemif",
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.parent = &pll1_sysclk5,
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.lpsc = DAVINCI_LPSC_AEMIF,
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};
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static struct clk pwm0_clk = {
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.name = "pwm0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM0,
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};
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static struct clk pwm1_clk = {
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.name = "pwm1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM1,
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};
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static struct clk pwm2_clk = {
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.name = "pwm2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_PWM2,
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};
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static struct clk timer0_clk = {
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.name = "timer0",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER0,
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};
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static struct clk timer1_clk = {
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.name = "timer1",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER1,
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};
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static struct clk timer2_clk = {
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.name = "timer2",
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.parent = &pll1_aux_clk,
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.lpsc = DAVINCI_LPSC_TIMER2,
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.usecount = 1, /* REVISIT: why can't this be disabled? */
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};
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static struct clk_lookup dm644x_clks[] = {
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CLK(NULL, "ref", &ref_clk),
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CLK(NULL, "pll1", &pll1_clk),
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CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
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CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
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CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
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CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
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CLK(NULL, "pll1_aux", &pll1_aux_clk),
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CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
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CLK(NULL, "pll2", &pll2_clk),
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CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
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CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
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CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
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CLK(NULL, "dsp", &dsp_clk),
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CLK(NULL, "arm", &arm_clk),
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CLK(NULL, "vicp", &vicp_clk),
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CLK("vpss", "master", &vpss_master_clk),
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CLK("vpss", "slave", &vpss_slave_clk),
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CLK(NULL, "arm", &arm_clk),
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//CLK("serial8250.0", NULL, &uart0_clk),
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CLK("1c20000.serial", NULL, &uart0_clk),
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CLK("serial8250.1", NULL, &uart1_clk),
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CLK("serial8250.2", NULL, &uart2_clk),
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//CLK("davinci_emac.1", NULL, &emac_clk),
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CLK("davinci_emac0", NULL, &emac_clk),
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CLK("davinci_mdio.0", "fck", &emac_clk),
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CLK("i2c_davinci.1", NULL, &i2c_clk),
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CLK("palm_bk3710", NULL, &ide_clk),
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CLK("davinci-mcbsp", NULL, &asp_clk),
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CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
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CLK(NULL, "spi", &spi_clk),
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CLK(NULL, "gpio", &gpio_clk),
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CLK(NULL, "usb", &usb_clk),
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CLK(NULL, "vlynq", &vlynq_clk),
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CLK(NULL, "aemif", &aemif_clk),
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CLK(NULL, "pwm0", &pwm0_clk),
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CLK(NULL, "pwm1", &pwm1_clk),
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CLK(NULL, "pwm2", &pwm2_clk),
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CLK(NULL, "timer0", &timer0_clk),
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CLK(NULL, "timer1", &timer1_clk),
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//CLK("davinci-wdt", NULL, &timer2_clk),
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CLK("1c21c00.wdt", NULL, &timer2_clk),
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CLK(NULL, NULL, NULL),
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};
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#if 0
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static struct emac_platform_data dm644x_emac_pdata = {
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.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
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.ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
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.ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
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.ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
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.version = EMAC_VERSION_1,
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};
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static struct resource dm644x_emac_resources[] = {
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{
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.start = DM644X_EMAC_BASE,
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.end = DM644X_EMAC_BASE + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_EMACINT,
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.end = IRQ_EMACINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device dm644x_emac_device = {
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.name = "davinci_emac",
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.id = 1,
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.dev = {
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.platform_data = &dm644x_emac_pdata,
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},
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.num_resources = ARRAY_SIZE(dm644x_emac_resources),
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.resource = dm644x_emac_resources,
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};
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static struct resource dm644x_mdio_resources[] = {
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{
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.start = DM644X_EMAC_MDIO_BASE,
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.end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device dm644x_mdio_device = {
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.name = "davinci_mdio",
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.id = 0,
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.num_resources = ARRAY_SIZE(dm644x_mdio_resources),
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.resource = dm644x_mdio_resources,
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};
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#endif
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static u32 dm644x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
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static struct davinci_soc_info davinci_soc_info_dm644x = {
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.cpu_clks = dm644x_clks,
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.psc_bases = dm644x_psc_bases,
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.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
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};
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static int dm644x_init(void)
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{
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davinci_common_init(&davinci_soc_info_dm644x);
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return 0;
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}
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postcore_initcall(dm644x_init);
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