303 lines
13 KiB
C
303 lines
13 KiB
C
/*
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* Based on Linux driver:
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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* Ported to Barebox:
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* Copyright (C) 2013 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AR2312_H
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#define AR2312_H
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#include <asm/addrspace.h>
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/* Address Map */
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#define AR2312_SDRAM0 0x00000000
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#define AR2312_SDRAM1 0x08000000
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#define AR2312_WLAN0 0x18000000
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#define AR2312_WLAN1 0x18500000
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#define AR2312_ENET0 0x18100000
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#define AR2312_ENET1 0x18200000
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#define AR2312_SDRAMCTL 0x18300000
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#define AR2312_FLASHCTL 0x18400000
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#define AR2312_APBBASE 0x1c000000
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#define AR2312_FLASH 0x1e000000
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#define AR2312_CPU_CLOCK_RATE 180000000
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/* Used by romSizeMemory to set SDRAM Memory Refresh */
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#define AR2312_SDRAM_CLOCK_RATE (AR2312_CPU_CLOCK_RATE / 2)
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/*
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* SDRAM Memory Refresh (MEM_REF) value is computed as:
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* 15.625us * SDRAM_CLOCK_RATE (in MHZ)
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*/
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#define DESIRED_MEMORY_REFRESH_NSECS 15625
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#define AR2312_SDRAM_MEMORY_REFRESH_VALUE \
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((DESIRED_MEMORY_REFRESH_NSECS * AR2312_SDRAM_CLOCK_RATE/1000000) / 1000)
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/*
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* APB Address Map
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*/
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#define AR2312_UART0 (AR2312_APBBASE + 0x0003) /* high speed uart */
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#define AR2312_UART_SHIFT 2
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#define AR2312_UART1 (AR2312_APBBASE + 0x1000) /* ar2312 only */
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#define AR2312_GPIO (AR2312_APBBASE + 0x2000)
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#define AR2312_RESETTMR (AR2312_APBBASE + 0x3000)
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#define AR2312_APB2AHB (AR2312_APBBASE + 0x4000)
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/*
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* AR2312_NUM_ENET_MAC defines the number of ethernet MACs that
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* should be considered available. The AR2312 supports 2 enet MACS,
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* even though many reference boards only actually use 1 of them
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* (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
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* The AR2312 supports 1 enet MAC.
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*/
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#define AR2312_NUM_ENET_MAC 2
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/*
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* Need these defines to determine true number of ethernet MACs
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*/
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#define AR5212_AR2312_REV2 0x52 /* AR2312 WMAC (AP31) */
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#define AR5212_AR2312_REV7 0x57 /* AR2312 WMAC (AP30-040) */
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#define AR5212_AR2313_REV8 0x58 /* AR2313 WMAC (AP43-030) */
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/* Reset/Timer Block Address Map */
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#define AR2312_RESETTMR (AR2312_APBBASE + 0x3000)
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#define AR2312_TIMER (AR2312_RESETTMR + 0x0000) /* countdown timer */
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#define AR2312_WD_CTRL (AR2312_RESETTMR + 0x0008) /* watchdog cntrl */
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#define AR2312_WD_TIMER (AR2312_RESETTMR + 0x000c) /* watchdog timer */
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#define AR2312_ISR (AR2312_RESETTMR + 0x0010) /* Intr Status Reg */
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#define AR2312_IMR (AR2312_RESETTMR + 0x0014) /* Intr Mask Reg */
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#define AR2312_RESET (AR2312_RESETTMR + 0x0020)
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#define AR2312_CLOCKCTL0 (AR2312_RESETTMR + 0x0060)
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#define AR2312_CLOCKCTL1 (AR2312_RESETTMR + 0x0064)
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#define AR2312_CLOCKCTL2 (AR2312_RESETTMR + 0x0068)
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#define AR2312_SCRATCH (AR2312_RESETTMR + 0x006c)
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#define AR2312_PROCADDR (AR2312_RESETTMR + 0x0070)
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#define AR2312_PROC1 (AR2312_RESETTMR + 0x0074)
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#define AR2312_DMAADDR (AR2312_RESETTMR + 0x0078)
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#define AR2312_DMA1 (AR2312_RESETTMR + 0x007c)
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#define AR2312_ENABLE (AR2312_RESETTMR + 0x0080) /* interface enb */
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#define AR2312_REV (AR2312_RESETTMR + 0x0090) /* revision */
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/* AR2312_WD_CTRL register bit field definitions */
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#define AR2312_WD_CTRL_IGNORE_EXPIRATION 0x0000
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#define AR2312_WD_CTRL_NMI 0x0001
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#define AR2312_WD_CTRL_RESET 0x0002
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/* AR2312_ISR register bit field definitions */
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#define AR2312_ISR_NONE 0x0000
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#define AR2312_ISR_TIMER 0x0001
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#define AR2312_ISR_AHBPROC 0x0002
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#define AR2312_ISR_AHBDMA 0x0004
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#define AR2312_ISR_GPIO 0x0008
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#define AR2312_ISR_UART0 0x0010
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#define AR2312_ISR_UART0DMA 0x0020
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#define AR2312_ISR_WD 0x0040
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#define AR2312_ISR_LOCAL 0x0080
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/* AR2312_RESET register bit field definitions */
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#define AR2312_RESET_SYSTEM 0x00000001 /* cold reset full system */
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#define AR2312_RESET_PROC 0x00000002 /* cold reset MIPS core */
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#define AR2312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
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#define AR2312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
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#define AR2312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
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#define AR2312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
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#define AR2312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
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#define AR2312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
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#define AR2312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
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#define AR2312_RESET_APB 0x00000400 /* cold reset APB (ar2312) */
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#define AR2312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
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#define AR2312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
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#define AR2312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
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#define AR2312_RESET_NMI 0x00010000 /* send an NMI to the processor */
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#define AR2312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
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#define AR2312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
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#define AR2312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
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#define AR2312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
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/* Values for AR2312_CLOCKCTL1
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*
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* The AR2312_CLOCKCTL1 register is loaded based on the speed of
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* our incoming clock. Currently, all valid configurations
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* for an AR2312 use an ar5112 radio clocked at 40MHz. Until
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* there are other configurations available, we'll hardcode
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* this 40MHz assumption.
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*/
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#define AR2312_INPUT_CLOCK 40000000
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#define AR2312_CLOCKCTL1_IN40_OUT160MHZ 0x0405 /* 40MHz in, 160Mhz out */
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#define AR2312_CLOCKCTL1_IN40_OUT180MHZ 0x0915 /* 40MHz in, 180Mhz out */
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#define AR2312_CLOCKCTL1_IN40_OUT200MHZ 0x1935 /* 40MHz in, 200Mhz out */
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#define AR2312_CLOCKCTL1_IN40_OUT220MHZ 0x0b15 /* 40MHz in, 220Mhz out */
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#define AR2312_CLOCKCTL1_IN40_OUT240MHZ 0x0605 /* 40MHz in, 240Mhz out */
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#define AR2312_CLOCKCTL1_SELECTION AR2312_CLOCKCTL1_IN40_OUT180MHZ
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#define AR2312_CPU_CLOCK_RATE 180000000
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/*
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* Special values for AR2313 'VIPER' PLL.
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*
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* These values do not match the latest datasheet for the AR2313,
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* which appears to be an exact copy of the AR2312 in this area.
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* The values were derived from the ECOS code provided in the Atheros
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* LSDK-1.0 (and confirmed by checking values on an AR2313 reference
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* design).
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*/
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#define AR2313_CLOCKCTL1_SELECTION 0x91245
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/* Bit fields for AR2312_CLOCKCTL2 */
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#define AR2312_CLOCKCTL2_WANT_RESET 0x00000001 /* reset with new vals */
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#define AR2312_CLOCKCTL2_WANT_DIV2 0x00000010 /* request /2 clock */
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#define AR2312_CLOCKCTL2_WANT_DIV4 0x00000020 /* request /4 clock */
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#define AR2312_CLOCKCTL2_WANT_PLL_BYPASS 0x00000080 /* request PLL bypass */
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#define AR2312_CLOCKCTL2_STATUS_DIV2 0x10000000 /* have /2 clock */
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#define AR2312_CLOCKCTL2_STATUS_DIV4 0x20000000 /* have /4 clock */
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#define AR2312_CLOCKCTL2_STATUS_PLL_BYPASS 0x80000000 /* PLL is bypassed */
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/* AR2312_CLOCKCTL1 register bit field definitions */
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#define AR2312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
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#define AR2312_CLOCKCTL1_PREDIVIDE_SHIFT 4
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#define AR2312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
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#define AR2312_CLOCKCTL1_MULTIPLIER_SHIFT 8
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#define AR2312_CLOCKCTL1_DOUBLER_MASK 0x00010000
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/* Valid for AR2313 */
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#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
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#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
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#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
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#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
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#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
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/* Values for AR2312_CLOCKCTL */
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#define AR2312_CLOCKCTL_ETH0 0x0004 /* enable eth0 clock */
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#define AR2312_CLOCKCTL_ETH1 0x0008 /* enable eth1 clock */
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#define AR2312_CLOCKCTL_UART0 0x0010 /* enable UART0 external clock */
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/* AR2312_ENABLE register bit field definitions */
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#define AR2312_ENABLE_ENET0 0x0002
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#define AR2312_ENABLE_ENET1 0x0004
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/* AR2312_REV register bit field definitions */
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#define AR2312_REV_WMAC_MAJ 0xf000
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#define AR2312_REV_WMAC_MAJ_S 12
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#define AR2312_REV_WMAC_MIN 0x0f00
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#define AR2312_REV_WMAC_MIN_S 8
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#define AR2312_REV_MAJ 0x00f0
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#define AR2312_REV_MAJ_S 4
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#define AR2312_REV_MIN 0x000f
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#define AR2312_REV_MIN_S 0
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#define AR2312_REV_CHIP (AR2312_REV_MAJ|AR2312_REV_MIN)
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/* Major revision numbers, bits 7..4 of Revision ID register */
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#define AR2312_REV_MAJ_AR2312 0x4
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#define AR2312_REV_MAJ_AR2313 0x5
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/* Minor revision numbers, bits 3..0 of Revision ID register */
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#define AR2312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
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#define AR2312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
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/* AR2312_FLASHCTL register bit field definitions */
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#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
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#define FLASHCTL_IDCY_S 0
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#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
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#define FLASHCTL_WST1_S 5
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#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
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#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
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#define FLASHCTL_WST2_S 11
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#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
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#define FLASHCTL_AC_S 16
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#define FLASHCTL_AC_128K 0x00000000
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#define FLASHCTL_AC_256K 0x00010000
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#define FLASHCTL_AC_512K 0x00020000
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#define FLASHCTL_AC_1M 0x00030000
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#define FLASHCTL_AC_2M 0x00040000
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#define FLASHCTL_AC_4M 0x00050000
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#define FLASHCTL_AC_8M 0x00060000
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#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
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#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
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#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
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#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
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#define FLASHCTL_WP 0x04000000 /* Write protect */
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#define FLASHCTL_BM 0x08000000 /* Burst mode */
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#define FLASHCTL_MW 0x30000000 /* Memory width */
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#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
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#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
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#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
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#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
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#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
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#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
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#define AR2312_MAX_FLASH_SIZE 0x800000
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/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
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#define AR2312_FLASHCTL0 (AR2312_FLASHCTL + 0x00)
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#define AR2312_FLASHCTL1 (AR2312_FLASHCTL + 0x04)
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#define AR2312_FLASHCTL2 (AR2312_FLASHCTL + 0x08)
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/* ARM SDRAM Controller -- just enough to determine memory size */
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#define AR2312_MEM_CFG0 (AR2312_SDRAMCTL + 0x00)
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#define AR2312_MEM_CFG1 (AR2312_SDRAMCTL + 0x04)
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#define AR2312_MEM_REF (AR2312_SDRAMCTL + 0x08) /* 16 bit value */
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#define MEM_CFG0_F0 0x00000002 /* bank 0: 256Mb support */
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#define MEM_CFG0_T0 0x00000004 /* bank 0: chip width */
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#define MEM_CFG0_B0 0x00000008 /* bank 0: 2 vs 4 bank */
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#define MEM_CFG0_F1 0x00000020 /* bank 1: 256Mb support */
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#define MEM_CFG0_T1 0x00000040 /* bank 1: chip width */
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#define MEM_CFG0_B1 0x00000080 /* bank 1: 2 vs 4 bank */
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/* bank 2 and 3 are not supported */
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#define MEM_CFG0_E 0x00020000 /* SDRAM clock control */
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#define MEM_CFG0_C 0x00040000 /* SDRAM clock enable */
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#define MEM_CFG0_X 0x00080000 /* bus width (0 == 32b) */
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#define MEM_CFG0_CAS 0x00300000 /* CAS latency (1-3) */
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#define MEM_CFG0_C1 0x00100000
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#define MEM_CFG0_C2 0x00200000
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#define MEM_CFG0_C3 0x00300000
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#define MEM_CFG0_R 0x00c00000 /* RAS to CAS latency (1-3) */
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#define MEM_CFG0_R1 0x00400000
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#define MEM_CFG0_R2 0x00800000
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#define MEM_CFG0_R3 0x00c00000
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#define MEM_CFG0_A 0x01000000 /* AHB auto pre-charge */
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#define MEM_CFG1_I 0x0001 /* memory init control */
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#define MEM_CFG1_M 0x0002 /* memory init control */
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#define MEM_CFG1_R 0x0004 /* read buffer enable (unused) */
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#define MEM_CFG1_W 0x0008 /* write buffer enable (unused) */
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#define MEM_CFG1_B 0x0010 /* SDRAM engine busy */
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#define MEM_CFG1_AC_2 0 /* AC of 2MB */
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#define MEM_CFG1_AC_4 1 /* AC of 4MB */
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#define MEM_CFG1_AC_8 2 /* AC of 8MB */
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#define MEM_CFG1_AC_16 3 /* AC of 16MB */
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#define MEM_CFG1_AC_32 4 /* AC of 32MB */
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#define MEM_CFG1_AC_64 5 /* AC of 64MB */
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#define MEM_CFG1_AC_128 6 /* AC of 128MB */
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#define MEM_CFG1_AC0_S 8
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#define MEM_CFG1_AC0 0x0700 /* bank 0: SDRAM addr check (added) */
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#define MEM_CFG1_E0 0x0800 /* bank 0: enable */
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#define MEM_CFG1_AC1_S 12
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#define MEM_CFG1_AC1 0x7000 /* bank 1: SDRAM addr check (added) */
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#define MEM_CFG1_E1 0x8000 /* bank 1: enable */
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/* GPIO Address Map */
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#define AR2312_GPIO (AR2312_APBBASE + 0x2000)
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#define AR2312_GPIO_DO (AR2312_GPIO + 0x00) /* output register */
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#define AR2312_GPIO_DI (AR2312_GPIO + 0x04) /* intput register */
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#define AR2312_GPIO_CR (AR2312_GPIO + 0x08) /* control register */
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/* GPIO Control Register bit field definitions */
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#define AR2312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
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#define AR2312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
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#define AR2312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
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#define AR2312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
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#define AR2312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
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#define AR2312_NUM_GPIO 8
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#endif
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