127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <init.h>
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#include <mach/fsl_i2c.h>
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#include <mach/immap_85xx.h>
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#include <mach/clock.h>
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#include <asm/io.h>
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#include <asm/fsl_lbc.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include "p1022ds.h"
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static const u8 spd_addr = 0x51;
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int fsl_ddr_board_info(struct ddr_board_info_s *info)
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{
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/*
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* Early mapping is needed to access the clock
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* parameters in the FPGA.
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*/
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p1022ds_lbc_early_init();
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info->fsl_ddr_ver = 0;
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info->ddr_base = IOMEM(MPC85xx_DDR_ADDR);
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/* Actual number of chip select used */
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info->cs_per_ctrl = CFG_CHIP_SELECTS_PER_CTRL;
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info->dimm_slots_per_ctrl = 1;
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info->i2c_bus = 1;
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info->i2c_slave = 0x7f;
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info->i2c_speed = 400000;
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info->i2c_base = IOMEM(I2C2_BASE_ADDR);
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info->spd_i2c_addr = &spd_addr;
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return 0;
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}
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust; /* Range: 0-8 */
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u32 cpo; /* Range: 2-31 */
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u32 write_data_delay; /* Range: 0-6 */
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u32 force_2t;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters dimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{ 1, 549, 5, 31, 3, 0 },
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{ 1, 850, 5, 31, 5, 0 },
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{ 2, 549, 5, 31, 3, 0 },
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{ 2, 850, 5, 31, 5, 0 },
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{ }
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};
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void fsl_ddr_board_options(struct memctl_options_s *popts,
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struct dimm_params_s *pdimm)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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unsigned long ddr_freq;
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uint32_t i;
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for (i = 0; i < popts->board_info->cs_per_ctrl; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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popts->cs_local_opts[i].odt_rtt_wr = DDR3_RTT_OFF;
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}
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popts->cs_local_opts[0].odt_rtt_norm = DDR3_RTT_40_OHM;
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popts->cs_local_opts[1].odt_rtt_norm = DDR3_RTT_OFF;
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pbsp = dimm0;
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ddr_freq = fsl_get_ddr_freq(0) / 1000000;
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/*
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* To have optimal parameters specific to the board, do a fine
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* adjustment of DDR parameters depending on the DDR data rate.
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*/
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->twoT_en = pbsp->force_2t;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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/* Use highest parameters if none were found */
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if (pbsp_highest) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->twoT_en = pbsp->force_2t;
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}
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found:
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popts->half_strength_driver_enable = 1;
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/* Per AN4039, enable ZQ calibration. */
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popts->zq_en = 1;
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popts->auto_self_refresh_en = 1;
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popts->sr_it = 0xb;
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popts->dll_rst_dis = 1;
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}
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