47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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/* decode S[0-2] to Output Divider (OD) */
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static u8 ics307_s_to_od[] = {
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10, 2, 8, 4, 5, 7, 3, 6
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};
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/* Calculate frequency being generated by ICS307-02 clock chip. */
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unsigned long ics307_clk_freq(unsigned int reg)
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{
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const unsigned long input_freq = 33333000;
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void __iomem *fpga_base = IOMEM(CFG_PIXIS_BASE);
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unsigned char cw0, cw1, cw2;
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unsigned long vdw, rdw, od, freq;
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cw0 = in_8(fpga_base + reg);
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cw1 = in_8(fpga_base + reg + 1);
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cw2 = in_8(fpga_base + reg + 2);
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vdw = ((cw1 << 1) & 0x1fe) + ((cw2 >> 7) & 1);
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rdw = cw2 & 0x7f;
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od = ics307_s_to_od[cw0 & 0x7];
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/*
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* CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
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*
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* cw0: C1 C0 TTL F1 F0 S2 S1 S0
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* cw1: V8 V7 V6 V5 V4 V3 V2 V1
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* cw2: V0 R6 R5 R4 R3 R2 R1 R0
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*
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* R6:R0 = Reference Divider Word (RDW)
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* V8:V0 = VCO Divider Word (VDW)
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* S2:S0 = Output Divider Select (OD)
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* F1:F0 = Function of CLK2 Output
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* TTL = duty cycle
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* C1:C0 = internal load capacitance for crystal
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*/
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freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
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return freq;
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}
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