89 lines
2.4 KiB
C
89 lines
2.4 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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*/
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/*
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* P2020RDB board configuration file
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CFG_SYS_CLK_FREQ get_board_sys_clk(0)
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#define CFG_DDR_CLK_FREQ 66666666
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xff700000
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#define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
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#define CFG_CCSRBAR_PHYS CFG_CCSRBAR
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#define CFG_IMMR CFG_CCSRBAR
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/* DDR Setup */
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#define CFG_CHIP_SELECTS_PER_CTRL 1
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#define CFG_SDRAM_BASE 0x00000000
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/* These timings are adjusted for a 667Mhz clock. */
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#define CFG_SYS_DDR_CS0_BNDS 0x0000003f /* 1GB */
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#define CFG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CFG_SYS_DDR_TIMING_3 0x00030000
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#define CFG_SYS_DDR_TIMING_0 0x55770802
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#define CFG_SYS_DDR_TIMING_1 0x5f599543
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#define CFG_SYS_DDR_TIMING_2 0x0fa074d1
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#define CFG_SYS_DDR_CONTROL 0xc3000000
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#define CFG_SYS_DDR_CONTROL2 0x24401000
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#define CFG_SYS_DDR_MODE_1 0x00040852
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#define CFG_SYS_DDR_MODE_2 0x00000000
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#define CFG_SYS_MD_CNTL 0x00000000
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#define CFG_SYS_DDR_INTERVAL 0x0a280100
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#define CFG_SYS_DDR_DATA_INIT 0xdeadbeef
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#define CFG_SYS_DDR_CLK_CTRL 0x03000000
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/*
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* Memory map
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*
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* 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
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*
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* Localbus non-cacheable
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* 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
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* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
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*/
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/*
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* Local Bus Definitions
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*/
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#define CFG_FLASH_BASE 0xef000000
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#define CFG_FLASH_BASE_PHYS CFG_FLASH_BASE
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#define CFG_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
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/* Leave 256 bytes for global data */
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#define CFG_INIT_SP_OFFSET (0x00004000 - 256)
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#endif /* __CONFIG_H */
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