117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
/*
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* Copyright 2013 GE Intelligent Platforms, Inc
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef FSL_DDR_MAIN_H
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#define FSL_DDR_MAIN_H
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <mach/fsl_i2c.h>
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#include <mach/clock.h>
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#include "common_timing_params.h"
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#ifdef CONFIG_MPC85xx
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#include <mach/immap_85xx.h>
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#endif
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/* Record of computed register values. */
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struct fsl_ddr_cfg_regs_s {
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struct {
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uint32_t bnds;
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uint32_t config;
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uint32_t config_2;
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} cs[MAX_CHIP_SELECTS_PER_CTRL];
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uint32_t timing_cfg_3;
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uint32_t timing_cfg_0;
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uint32_t timing_cfg_1;
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uint32_t timing_cfg_2;
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uint32_t ddr_sdram_cfg;
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uint32_t ddr_sdram_cfg_2;
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uint32_t ddr_sdram_mode;
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uint32_t ddr_sdram_mode_2;
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uint32_t ddr_sdram_mode_3;
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uint32_t ddr_sdram_mode_4;
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uint32_t ddr_sdram_mode_5;
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uint32_t ddr_sdram_mode_6;
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uint32_t ddr_sdram_mode_7;
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uint32_t ddr_sdram_mode_8;
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uint32_t ddr_sdram_md_cntl;
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uint32_t ddr_sdram_interval;
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uint32_t ddr_data_init;
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uint32_t ddr_sdram_clk_cntl;
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uint32_t ddr_init_addr;
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uint32_t ddr_init_ext_addr;
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uint32_t timing_cfg_4;
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uint32_t timing_cfg_5;
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uint32_t ddr_zq_cntl;
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uint32_t ddr_wrlvl_cntl;
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uint32_t ddr_wrlvl_cntl_2;
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uint32_t ddr_wrlvl_cntl_3;
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uint32_t ddr_sr_cntr;
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uint32_t ddr_sdram_rcw_1;
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uint32_t ddr_sdram_rcw_2;
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uint32_t ddr_cdr1;
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uint32_t ddr_cdr2;
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uint32_t err_disable;
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uint32_t err_int_en;
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uint32_t debug[32];
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};
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/*
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* Data Structures
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*
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* All data structures have to be on the stack
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*/
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struct fsl_ddr_info_s {
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generic_spd_eeprom_t
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spd_installed_dimms[MAX_DIMM_SLOTS_PER_CTLR];
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struct dimm_params_s
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dimm_params[MAX_DIMM_SLOTS_PER_CTLR];
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struct memctl_options_s memctl_opts;
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struct common_timing_params_s common_timing_params;
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struct fsl_ddr_cfg_regs_s fsl_ddr_config_reg;
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struct ddr_board_info_s board_info;
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};
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uint32_t mclk_to_picos(uint32_t mclk);
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uint32_t get_memory_clk_period_ps(void);
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uint32_t picos_to_mclk(uint32_t picos);
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uint32_t check_fsl_memctl_config_regs(const struct fsl_ddr_cfg_regs_s *ddr);
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uint64_t fsl_ddr_compute(struct fsl_ddr_info_s *pinfo);
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uint32_t compute_fsl_memctl_config_regs(
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const struct memctl_options_s *popts,
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struct fsl_ddr_cfg_regs_s *ddr,
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const struct common_timing_params_s *common_dimm,
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const struct dimm_params_s *dimm_parameters,
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uint32_t dbw_capacity_adjust);
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uint32_t compute_dimm_parameters(
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const generic_spd_eeprom_t *spdin,
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struct dimm_params_s *pdimm);
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void compute_lowest_common_dimm_parameters(
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const struct fsl_ddr_info_s *pinfo,
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struct common_timing_params_s *outpdimm,
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uint32_t number_of_dimms);
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uint32_t populate_memctl_options(
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int all_DIMMs_registered,
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struct memctl_options_s *popts,
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struct dimm_params_s *pdimm);
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int fsl_ddr_set_lawbar(
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const struct common_timing_params_s *memctl_common_params,
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uint32_t memctl_interleaved);
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int fsl_ddr_get_spd(
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generic_spd_eeprom_t *ctrl_dimms_spd,
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struct ddr_board_info_s *binfo);
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int fsl_ddr_set_memctl_regs(
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const struct fsl_ddr_info_s *info);
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void fsl_ddr_board_options(
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struct memctl_options_s *popts,
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struct dimm_params_s *pdimm);
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void fsl_ddr_board_info(struct ddr_board_info_s *info);
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#endif
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