256 lines
7.2 KiB
C
256 lines
7.2 KiB
C
/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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static uint32_t
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compute_cas_latency_ddr3(const struct dimm_params_s *dimm_params,
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uint32_t number_of_dimms)
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{
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uint32_t i, taamin_ps = 0, tckmin_x_ps = 0, common_caslat,
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caslat_actual, retry = 16;
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const uint32_t mclk_ps = get_memory_clk_period_ps();
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/* compute the common CAS latency supported between slots */
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common_caslat = dimm_params[0].caslat_X;
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for (i = 1; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks)
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common_caslat &= dimm_params[i].caslat_X;
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}
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for (i = 0; i < number_of_dimms; i++) {
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taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
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tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tCKmin_X_ps);
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}
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caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
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/* check if the dimms support the CAS latency */
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while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
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caslat_actual++;
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retry--;
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}
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return caslat_actual;
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}
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static unsigned int common_burst_length(
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const struct dimm_params_s *dimm_params,
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const unsigned int number_of_dimms)
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{
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unsigned int i, temp;
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temp = 0xff;
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for (i = 0; i < number_of_dimms; i++)
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if (dimm_params[i].n_ranks)
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temp &= dimm_params[i].burst_lengths_bitmask;
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return temp;
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}
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/* Compute a CAS latency suitable for all DIMMs */
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static unsigned int compute_lowest_caslat(
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const struct dimm_params_s *dimm_params,
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const unsigned int number_of_dimms)
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{
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uint32_t temp1, temp2, i, not_ok, lowest_good_caslat,
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tCKmin_X_minus_1_ps, tCKmin_X_minus_2_ps;
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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/*
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* Step 1: find CAS latency common to all DIMMs using bitwise
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* operation.
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*/
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temp1 = 0xFF;
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for (i = 0; i < number_of_dimms; i++)
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if (dimm_params[i].n_ranks) {
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temp2 = 0;
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temp2 |= 1 << dimm_params[i].caslat_X;
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temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
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temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
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/*
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* FIXME: If there was no entry for X-2 (X-1) in
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* the SPD, then caslat_X_minus_2
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* (caslat_X_minus_1) contains either 255 or
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* 0xFFFFFFFF because that's what the __ilog2
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* function returns for an input of 0.
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* On 32-bit PowerPC, left shift counts with bit
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* 26 set (that the value of 255 or 0xFFFFFFFF
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* will have), cause the destination register to
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* be 0. That is why this works.
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*/
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temp1 &= temp2;
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}
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/*
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* Step 2: check each common CAS latency against tCK of each
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* DIMM's SPD.
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*/
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lowest_good_caslat = 0;
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temp2 = 0;
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while (temp1) {
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not_ok = 0;
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temp2 = __ilog2(temp1);
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for (i = 0; i < number_of_dimms; i++) {
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if (!dimm_params[i].n_ranks)
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continue;
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if (dimm_params[i].caslat_X == temp2) {
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if (mclk_ps >= dimm_params[i].tCKmin_X_ps)
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continue;
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else
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not_ok++;
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}
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if (dimm_params[i].caslat_X_minus_1 == temp2) {
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tCKmin_X_minus_1_ps =
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dimm_params[i].tCKmin_X_minus_1_ps;
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if (mclk_ps >= tCKmin_X_minus_1_ps)
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continue;
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else
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not_ok++;
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}
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if (dimm_params[i].caslat_X_minus_2 == temp2) {
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tCKmin_X_minus_2_ps
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= dimm_params[i].tCKmin_X_minus_2_ps;
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if (mclk_ps >= tCKmin_X_minus_2_ps)
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continue;
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else
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not_ok++;
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}
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}
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if (!not_ok)
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lowest_good_caslat = temp2;
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temp1 &= ~(1 << temp2);
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}
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return lowest_good_caslat;
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}
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/*
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* compute_lowest_common_dimm_parameters()
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*
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* Determine the worst-case DIMM timing parameters from the set of DIMMs
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* whose parameters have been computed into the array pointed to
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* by dimm_params.
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*/
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void compute_lowest_common_dimm_parameters(const struct fsl_ddr_info_s *pinfo,
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struct common_timing_params_s *out,
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const unsigned int number_of_dimms)
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{
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uint32_t temp1, i;
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struct common_timing_params_s tmp = {0};
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const struct dimm_params_s *dimm = pinfo->dimm_params;
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const struct memctl_options_s *popts = &pinfo->memctl_opts;
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tmp.tCKmax_ps = 0xFFFFFFFF;
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tmp.extended_op_srt = 1;
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm[i].n_ranks == 0) {
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temp1++;
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continue;
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}
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/*
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* Find minimum tCKmax_ps to find fastest slow speed,
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* i.e., this is the slowest the whole system can go.
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*/
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tmp.tCKmax_ps = min(tmp.tCKmax_ps, dimm[i].tCKmax_ps);
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/* Find maximum value to determine slowest speed, delay, etc */
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tmp.tCKmin_X_ps = max(tmp.tCKmin_X_ps, dimm[i].tCKmin_X_ps);
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tmp.tCKmax_max_ps = max(tmp.tCKmax_max_ps, dimm[i].tCKmax_ps);
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tmp.tRCD_ps = max(tmp.tRCD_ps, dimm[i].tRCD_ps);
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tmp.tRP_ps = max(tmp.tRP_ps, dimm[i].tRP_ps);
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tmp.tRAS_ps = max(tmp.tRAS_ps, dimm[i].tRAS_ps);
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tmp.tWR_ps = max(tmp.tWR_ps, dimm[i].tWR_ps);
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tmp.tWTR_ps = max(tmp.tWTR_ps, dimm[i].tWTR_ps);
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tmp.tRFC_ps = max(tmp.tRFC_ps, dimm[i].tRFC_ps);
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tmp.tRRD_ps = max(tmp.tRRD_ps, dimm[i].tRRD_ps);
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tmp.tRC_ps = max(tmp.tRC_ps, dimm[i].tRC_ps);
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tmp.tIS_ps = max(tmp.tIS_ps, dimm[i].tIS_ps);
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tmp.tIH_ps = max(tmp.tIH_ps, dimm[i].tIH_ps);
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tmp.tDS_ps = max(tmp.tDS_ps, dimm[i].tDS_ps);
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tmp.tDH_ps = max(tmp.tDH_ps, dimm[i].tDH_ps);
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tmp.tRTP_ps = max(tmp.tRTP_ps, dimm[i].tRTP_ps);
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tmp.tQHS_ps = max(tmp.tQHS_ps, dimm[i].tQHS_ps);
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tmp.refresh_rate_ps = max(tmp.refresh_rate_ps,
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dimm[i].refresh_rate_ps);
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tmp.extended_op_srt = min(tmp.extended_op_srt,
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dimm[i].extended_op_srt);
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/* Find maximum tDQSQ_max_ps to find slowest timing. */
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tmp.tDQSQ_max_ps = max(tmp.tDQSQ_max_ps, dimm[i].tDQSQ_max_ps);
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}
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tmp.ndimms_present = number_of_dimms - temp1;
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if (temp1 == number_of_dimms)
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return;
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temp1 = common_burst_length(dimm, number_of_dimms);
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tmp.all_DIMMs_burst_lengths_bitmask = temp1;
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/* Support only unbuffered DIMMs */
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tmp.all_DIMMs_registered = 0;
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tmp.all_DIMMs_unbuffered = 1;
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if (popts->sdram_type == SDRAM_TYPE_DDR3) {
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tmp.lowest_common_SPD_caslat = compute_cas_latency_ddr3(dimm,
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number_of_dimms);
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} else {
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tmp.lowest_common_SPD_caslat = compute_lowest_caslat(dimm,
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number_of_dimms);
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/*
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* Compute a common 'de-rated' CAS latency.
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*
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* The strategy here is to find the *highest* de-rated cas
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* latency with the assumption that all of the DIMMs will
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* support a de-rated CAS latency higher than or equal to
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* their lowest de-rated value.
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*/
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++)
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temp1 = max(temp1, dimm[i].caslat_lowest_derated);
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tmp.highest_common_derated_caslat = temp1;
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}
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temp1 = 1;
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for (i = 0; i < number_of_dimms; i++)
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if (dimm[i].n_ranks && !(dimm[i].edc_config & EDC_ECC)) {
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temp1 = 0;
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break;
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}
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tmp.all_DIMMs_ECC_capable = temp1;
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/*
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* AL must be less or equal to tRCD. Typically, AL would
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* be AL = tRCD - 1;
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*
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* When ODT read or write is enabled the sum of CAS latency +
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* additive latency must be at least 3 cycles.
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*/
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tmp.additive_latency = 0;
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if (popts->sdram_type == SDRAM_TYPE_DDR2) {
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if ((tmp.lowest_common_SPD_caslat < 4) &&
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(picos_to_mclk(tmp.tRCD_ps) >
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tmp.lowest_common_SPD_caslat))
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tmp.additive_latency = picos_to_mclk(tmp.tRCD_ps) -
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tmp.lowest_common_SPD_caslat;
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if (mclk_to_picos(tmp.additive_latency) > tmp.tRCD_ps)
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tmp.additive_latency = picos_to_mclk(tmp.tRCD_ps);
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}
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memcpy(out, &tmp, sizeof(struct common_timing_params_s));
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}
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