148 lines
3.9 KiB
C
148 lines
3.9 KiB
C
/*
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* Copyright 2008, 2010-2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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uint32_t populate_memctl_options(int all_DIMMs_registered,
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struct memctl_options_s *popts,
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struct dimm_params_s *pdimm)
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{
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const struct ddr_board_info_s *binfo = popts->board_info;
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uint32_t i;
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for (i = 0; i < binfo->cs_per_ctrl; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
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popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_ALL;
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popts->cs_local_opts[i].odt_rtt_norm = DDR2_RTT_50_OHM;
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popts->cs_local_opts[i].odt_rtt_wr = DDR2_RTT_OFF;
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popts->cs_local_opts[i].auto_precharge = 0;
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}
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/* Memory Organization Parameters */
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popts->registered_dimm_en = all_DIMMs_registered;
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popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
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popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
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/* Choose DQS config - 1 for DDR2 */
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popts->DQS_config = 1;
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/* Choose self-refresh during sleep. */
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popts->self_refresh_in_sleep = 1;
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/* Choose dynamic power management mode. */
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popts->dynamic_power = 0;
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/*
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* check first dimm for primary sdram width
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* assuming all dimms are similar
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* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
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*/
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if (pdimm->n_ranks != 0) {
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if (popts->sdram_type == SDRAM_TYPE_DDR3) {
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if (pdimm[0].primary_sdram_width == 64)
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popts->data_bus_width = 0;
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else if (pdimm[0].primary_sdram_width == 32)
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popts->data_bus_width = 1;
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else if (pdimm[0].primary_sdram_width == 16)
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popts->data_bus_width = 2;
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else
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hang();
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} else {
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if ((pdimm->data_width >= 64) &&
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(pdimm->data_width <= 72))
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popts->data_bus_width = 0;
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else if ((pdimm->data_width >= 32) &&
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(pdimm->data_width <= 40))
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popts->data_bus_width = 1;
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else
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hang();
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}
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}
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if (popts->sdram_type == SDRAM_TYPE_DDR3) {
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if (popts->data_bus_width == 0) {
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popts->otf_burst_chop_en = 1;
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popts->burst_length = DDR_OTF;
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} else {
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/* 32-bit or 16-bit bus */
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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}
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popts->mirrored_dimm = pdimm[0].mirrored_dimm;
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} else {
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/* Must be a burst length of 4 for DDR2 */
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popts->burst_length = DDR_BL4;
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}
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/* Decide whether to use the computed de-rated latency */
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popts->use_derated_caslat = 0;
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/*
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* 2T_EN setting
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*
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* Factors to consider for 2T_EN:
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* - number of DIMMs installed
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* - number of components, number of active ranks
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* - how much time you want to spend playing around
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*/
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popts->twoT_en = 0;
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popts->threet_en = 0;
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/*
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* Default BSTTOPRE precharge interval
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*
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* Set the parameter to 0 for global auto precharge in
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* the board options function.
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*/
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popts->bstopre = 0x100;
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/* Minimum CKE pulse width -- tCKE(MIN) */
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popts->tCKE_clock_pulse_width_ps
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= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
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/*
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* Window for four activates -- tFAW
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*
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* Set according to specification for the memory used.
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* The default value below would work for x4/x8 wide memory.
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*
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*/
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if (popts->sdram_type == SDRAM_TYPE_DDR2) {
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popts->tFAW_window_four_activates_ps = 37500;
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} else {
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/*
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* Due to ddr3 dimm fly-by topology, enable write leveling
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* to meet the tQDSS under different loading.
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*/
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popts->tFAW_window_four_activates_ps = pdimm[0].tfaw_ps;
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popts->wrlvl_en = 1;
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popts->zq_en = 1;
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popts->wrlvl_override = 0;
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}
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/*
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* Default powerdown exit timings.
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* Set according to specifications for the memory used in
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* the board options function.
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*/
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popts->txard = 3;
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popts->txp = 3;
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popts->taxpd = 11;
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/* Default value for load mode cycle time */
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popts->tmrd = 2;
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/* Specific board override parameters. */
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fsl_ddr_board_options(popts, pdimm);
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return 0;
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}
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