188 lines
4.9 KiB
C
188 lines
4.9 KiB
C
/*
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* Copyright 2012 GE Intelligent Platforms, Inc.
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef FSL_DDR_MEMCTL_H
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#define FSL_DDR_MEMCTL_H
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#include <ddr_spd.h>
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/* Basic DDR Technology. */
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#define SDRAM_TYPE_DDR1 2
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#define SDRAM_TYPE_DDR2 3
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#define SDRAM_TYPE_LPDDR1 6
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#define SDRAM_TYPE_DDR3 7
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#define DDR_BL4 4
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#define DDR_BC4 DDR_BL4
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#define DDR_OTF 6
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#define DDR_BL8 8
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#define DDR2_RTT_OFF 0
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#define DDR2_RTT_75_OHM 1
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#define DDR2_RTT_150_OHM 2
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#define DDR2_RTT_50_OHM 3
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#define DDR3_RTT_OFF 0
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#define DDR3_RTT_40_OHM 3
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#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3)
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#if defined(CONFIG_FSL_DDR2)
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typedef struct ddr2_spd_eeprom_s generic_spd_eeprom_t;
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#define FSL_SDRAM_TYPE SDRAM_TYPE_DDR2
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#elif defined(CONFIG_FSL_DDR3)
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typedef struct ddr3_spd_eeprom_s generic_spd_eeprom_t;
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#define FSL_SDRAM_TYPE SDRAM_TYPE_DDR3
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#endif
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#define FSL_DDR_ODT_NEVER 0x0
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#define FSL_DDR_ODT_CS 0x1
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#define FSL_DDR_ODT_ALL_OTHER_CS 0x2
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#define FSL_DDR_ODT_OTHER_DIMM 0x3
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#define FSL_DDR_ODT_ALL 0x4
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#define FSL_DDR_ODT_SAME_DIMM 0x5
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#define FSL_DDR_ODT_CS_AND_OTHER_DIMM 0x6
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#define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
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#define SDRAM_CS_CONFIG_EN 0x80000000
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/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration */
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#define SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG_SREN 0x40000000
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#define SDRAM_CFG_ECC_EN 0x20000000
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#define SDRAM_CFG_RD_EN 0x10000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
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#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
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#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
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#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
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#define SDRAM_CFG_DYN_PWR 0x00200000
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#define SDRAM_CFG_32_BE 0x00080000
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#define SDRAM_CFG_16_BE 0x00100000
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#define SDRAM_CFG_8_BE 0x00040000
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#define SDRAM_CFG_NCAP 0x00020000
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#define SDRAM_CFG_2T_EN 0x00008000
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#define SDRAM_CFG_BI 0x00000001
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
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#define SDRAM_CFG2_ODT_NEVER 0
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#define SDRAM_CFG2_ODT_ONLY_WRITE 1
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#define SDRAM_CFG2_ODT_ONLY_READ 2
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#define SDRAM_CFG2_ODT_ALWAYS 3
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#define MAX_CHIP_SELECTS_PER_CTRL 4
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#define MAX_DIMM_SLOTS_PER_CTLR 4
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/*
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* Memory controller characteristics and I2C parameters to
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* read the SPD data.
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*/
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struct ddr_board_info_s {
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uint32_t fsl_ddr_ver;
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void __iomem *ddr_base;
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uint32_t cs_per_ctrl;
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uint32_t dimm_slots_per_ctrl;
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uint32_t i2c_bus;
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uint32_t i2c_slave;
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uint32_t i2c_speed;
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void __iomem *i2c_base;
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uint8_t *spd_i2c_addr;
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};
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/*
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* Generalized parameters for memory controller configuration,
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* might be a little specific to the FSL memory controller
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*/
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struct memctl_options_s {
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struct ddr_board_info_s *board_info;
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uint32_t sdram_type;
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/*
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* Memory organization parameters
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*
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* if DIMM is present in the system
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* where DIMMs are with respect to chip select
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* where chip selects are with respect to memory boundaries
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*/
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uint32_t registered_dimm_en;
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/* Options local to a Chip Select */
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struct cs_local_opts_s {
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uint32_t auto_precharge;
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uint32_t odt_rd_cfg;
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uint32_t odt_wr_cfg;
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uint32_t odt_rtt_norm;
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uint32_t odt_rtt_wr;
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} cs_local_opts[MAX_CHIP_SELECTS_PER_CTRL];
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/* DLL reset disable */
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uint32_t dll_rst_dis;
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/* Operational mode parameters */
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uint32_t ECC_mode;
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uint32_t ECC_init_using_memctl;
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uint32_t data_init;
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/* Use DQS? maybe only with DDR2? */
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uint32_t DQS_config;
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uint32_t self_refresh_in_sleep;
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uint32_t dynamic_power;
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uint32_t data_bus_width;
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uint32_t burst_length;
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uint32_t otf_burst_chop_en;
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uint32_t mirrored_dimm;
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uint32_t ap_en;
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uint32_t x4_en;
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/* Global Timing Parameters */
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uint32_t cas_latency_override;
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uint32_t cas_latency_override_value;
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uint32_t use_derated_caslat;
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uint32_t additive_latency_override;
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uint32_t additive_latency_override_value;
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uint32_t clk_adjust;
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uint32_t cpo_override;
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uint32_t write_data_delay;
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/* Write leveling */
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uint32_t wrlvl_override;
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uint32_t wrlvl_sample;
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uint32_t wrlvl_start;
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uint32_t wrlvl_ctl_2;
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uint32_t wrlvl_ctl_3;
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uint32_t half_strength_driver_enable;
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uint32_t twoT_en;
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uint32_t threet_en;
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uint32_t bstopre;
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uint32_t tCKE_clock_pulse_width_ps;
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uint32_t tFAW_window_four_activates_ps;
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/* Rtt impedance */
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uint32_t rtt_override;
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uint32_t rtt_override_value;
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uint32_t rtt_wr_override_value;
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/* Automatic self refresh */
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uint32_t auto_self_refresh_en;
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uint32_t sr_it;
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/* ZQ calibration */
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uint32_t zq_en;
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/* Write leveling */
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uint32_t wrlvl_en;
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/* RCW override for RDIMM */
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uint32_t rcw_override;
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uint32_t rcw_1;
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uint32_t rcw_2;
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/* control register 1 */
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uint32_t ddr_cdr1;
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uint32_t ddr_cdr2;
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/* read-to-write turnaround */
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uint32_t trwt_override;
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uint32_t trwt;
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/* Powerdon timings. */
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uint32_t txp;
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uint32_t taxpd;
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uint32_t txard;
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/* Load mode cycle time */
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uint32_t tmrd;
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};
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extern phys_size_t fsl_ddr_sdram(void);
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extern phys_size_t fixed_sdram(void);
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#endif
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