194 lines
6.6 KiB
C
194 lines
6.6 KiB
C
/*
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* MPC85xx Internal Memory Map
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*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* Copyright(c) 2002,2003 Motorola Inc.
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* Xianghua Xiao (x.xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __IMMAP_85xx__
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#define __IMMAP_85xx__
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#include <asm/types.h>
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#include <asm/fsl_lbc.h>
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#include <asm/config.h>
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#define MPC85xx_LOCAL_OFFSET 0x0000
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#define MPC85xx_ECM_OFFSET 0x1000
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#define MPC85xx_DDR_OFFSET 0x2000
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#define MPC85xx_LBC_OFFSET 0x5000
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#define MPC85xx_PCI1_OFFSET 0x8000
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#define MPC85xx_GPIO_OFFSET 0xf000
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#define MPC85xx_L2_OFFSET 0x20000
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#ifdef FSL_TSECV2
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#define TSEC1_OFFSET 0xB0000
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#else
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#define TSEC1_OFFSET 0x24000
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#endif
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#define MPC85xx_PIC_OFFSET 0x40000
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#define MPC85xx_GUTS_OFFSET 0xe0000
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#define MPC85xx_LOCAL_ADDR (CFG_IMMR + MPC85xx_LOCAL_OFFSET)
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#define MPC85xx_ECM_ADDR (CFG_IMMR + MPC85xx_ECM_OFFSET)
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#define MPC85xx_GUTS_ADDR (CFG_IMMR + MPC85xx_GUTS_OFFSET)
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#define MPC85xx_DDR_ADDR (CFG_IMMR + MPC85xx_DDR_OFFSET)
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#define LBC_ADDR (CFG_IMMR + MPC85xx_LBC_OFFSET)
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#define MPC85xx_GPIO_ADDR (CFG_IMMR + MPC85xx_GPIO_OFFSET)
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#define MPC85xx_L2_ADDR (CFG_IMMR + MPC85xx_L2_OFFSET)
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#define MPC8xxx_PIC_ADDR (CFG_IMMR + MPC85xx_PIC_OFFSET)
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/* Local-Access Registers */
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#define MPC85xx_LOCAL_BPTR_OFFSET 0x20 /* Boot Page Translation */
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/* ECM Registers */
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#define MPC85xx_ECM_EEBPCR_OFFSET 0x00 /* ECM CCB Port Configuration */
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#define MPC85xx_ECM_EEDR_OFFSET 0xE00 /* ECM error detect register */
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#define MPC85xx_ECM_EEER_OFFSET 0xE08 /* ECM error enable register */
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/*
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* DDR Memory Controller Register Offsets
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*/
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/* Chip Select 0, 1,2, 3 Memory Bounds */
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#define MPC85xx_DDR_CS0_BNDS_OFFSET 0x000
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#define MPC85xx_DDR_CS1_BNDS_OFFSET 0x008
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#define MPC85xx_DDR_CS2_BNDS_OFFSET 0x010
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#define MPC85xx_DDR_CS3_BNDS_OFFSET 0x018
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/* Chip Select 0, 1, 2, 3 Configuration */
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#define MPC85xx_DDR_CS0_CONFIG_OFFSET 0x080
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#define MPC85xx_DDR_CS1_CONFIG_OFFSET 0x084
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#define MPC85xx_DDR_CS2_CONFIG_OFFSET 0x088
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#define MPC85xx_DDR_CS3_CONFIG_OFFSET 0x08c
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/* Chip Select 0, 1, 2, 3 Configuration 2 */
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#define MPC85xx_DDR_CS0_CONFIG_2_OFFSET 0x0c0
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#define MPC85xx_DDR_CS1_CONFIG_2_OFFSET 0x0c4
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#define MPC85xx_DDR_CS2_CONFIG_2_OFFSET 0x0c8
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#define MPC85xx_DDR_CS3_CONFIG_2_OFFSET 0x0cc
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/* SDRAM Timing Configuration 0, 1, 2, 3 */
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#define MPC85xx_DDR_TIMING_CFG_3_OFFSET 0x100
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#define MPC85xx_DDR_TIMING_CFG_0_OFFSET 0x104
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#define MPC85xx_DDR_TIMING_CFG_1_OFFSET 0x108
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#define MPC85xx_DDR_TIMING_CFG_2_OFFSET 0x10c
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/* SDRAM Control Configuration */
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#define MPC85xx_DDR_SDRAM_CFG_OFFSET 0x110
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#define MPC85xx_DDR_SDRAM_CFG_2_OFFSET 0x114
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/* SDRAM Mode Configuration */
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#define MPC85xx_DDR_SDRAM_MODE_OFFSET 0x118
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#define MPC85xx_DDR_SDRAM_MODE_2_OFFSET 0x11c
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/* SDRAM Mode Control */
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#define MPC85xx_DDR_SDRAM_MD_CNTL_OFFSET 0x120
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/* SDRAM Interval Configuration */
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#define MPC85xx_DDR_SDRAM_INTERVAL_OFFSET 0x124
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/* SDRAM Data initialization */
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#define MPC85xx_DDR_SDRAM_DATA_INIT_OFFSET 0x128
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/* SDRAM Clock Control */
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#define MPC85xx_DDR_SDRAM_CLK_CNTL_OFFSET 0x130
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/* training init and extended addr */
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#define MPC85xx_DDR_SDRAM_INIT_ADDR_OFFSET 0x148
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#define MPC85xx_DDR_SDRAM_INIT_ADDR_EXT_OFFSET 0x14c
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/* SDRAM Timing Configuration 4,5 */
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#define MPC85xx_DDR_TIMING_CFG_4_OFFSET 0x160
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#define MPC85xx_DDR_TIMING_CFG_5_OFFSET 0x164
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/* DDR ZQ calibration control */
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#define MPC85xx_DDR_ZQ_CNTL_OFFSET 0x170
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/* DDR write leveling control */
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#define MPC85xx_DDR_WRLVL_CNTL_OFFSET 0x174
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/* Self Refresh Counter */
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#define MPC85xx_DDR_SR_CNTL_OFFSET 0x17c
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/* DDR SDRAM Register Control Word */
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#define MPC85xx_DDR_SDRAM_RCW_1_OFFSET 0x180
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#define MPC85xx_DDR_SDRAM_RCW_2_OFFSET 0x184
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/* DDR write leveling control */
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#define MPC85xx_DDR_WRLVL_CNTL_2_OFFSET 0x190
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#define MPC85xx_DDR_WRLVL_CNTL_3_OFFSET 0x194
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/* DDR Control Driver */
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#define MPC85xx_DDR_DDRCDR1_OFFSET 0xb28
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#define MPC85xx_DDR_DDRCDR2_OFFSET 0xb2c
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/* DDR IP block revision */
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#define MPC85xx_DDR_IP_REV1_OFFSET 0xbf8
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#define MPC85xx_DDR_IP_REV2_OFFSET 0xbfc
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/* Memory Error Disable */
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#define MPC85xx_DDR_ERR_DISABLE_OFFSET 0xe44
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#define MPC85xx_DDR_ERR_INT_EN_OFFSET 0xe48
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#define DDR_OFF(REGNAME) (MPC85xx_DDR_##REGNAME##_OFFSET)
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/*
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* GPIO Register Offsets
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*/
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#define MPC85xx_GPIO_GPDIR 0x00
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#define MPC85xx_GPIO_GPDAT 0x08
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#define MPC85xx_GPIO_GPDIR_OFFSET 0x00
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#define MPC85xx_GPIO_GPDAT_OFFSET 0x08
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/* Global Utilities Registers */
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#define MPC85xx_GPIOCR_OFFSET 0x30
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#define MPC85xx_GPIOCR_GPOUT 0x00000200
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#define MPC85xx_GPOUTDR_OFFSET 0x40
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#define MPC85xx_GPIOBIT(i) (1 << (31 - i))
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#define MPC85xx_GPINDR_OFFSET 0x50
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#define MPC85xx_DEVDISR_OFFSET 0x70
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#define MPC85xx_DEVDISR_TSEC1 0x00000080
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#define MPC85xx_DEVDISR_TSEC2 0x00000040
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#define MPC85xx_DEVDISR_TSEC3 0x00000020
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/*
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* L2 Cache Register Offsets
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*/
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#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */
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#define MPC85xx_L2CTL_L2E 0x80000000
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/* PIC registers offsets */
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#define MPC85xx_PIC_WHOAMI_OFFSET 0x090
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#define MPC85xx_PIC_FRR_OFFSET 0x1000 /* Feature Reporting */
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/* PIC registers fields values and masks. */
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#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
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#define MPC8xxx_PICFRR_NCPU_SHIFT 8
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#define MPC85xx_PICGCR_RST 0x80000000
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#define MPC85xx_PICGCR_M 0x20000000
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#define MPC85xx_PIC_IACK0_OFFSET 0x600a0 /* IRQ Acknowledge for
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Processor 0 */
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/* Global Utilities Register Offsets and field values */
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#define MPC85xx_GUTS_PORPLLSR_OFFSET 0x0
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#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
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#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
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#define MPC85xx_GUTS_PORDEVSR2_OFFSET 0x14
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#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
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#define MPC85xx_GUTS_PMUXCR_OFFSET 0x60
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#define MPC85xx_GUTS_PMUXCR2_OFFSET 0x64
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#define MPC85xx_GUTS_DEVDISR_OFFSET 0x70
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#define MPC85xx_DEVDISR_TB0 0x00004000
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#define MPC85xx_DEVDISR_TB1 0x00001000
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#define MPC85xx_GUTS_RSTCR_OFFSET 0xb0
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#define GFAR_BASE_ADDR (CFG_IMMR + TSEC1_OFFSET)
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#define MDIO_BASE_ADDR (CFG_IMMR + 0x24000)
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#define I2C1_BASE_ADDR (CFG_IMMR + 0x3000)
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#define I2C2_BASE_ADDR (CFG_IMMR + 0x3100)
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/* Global Timer Registers */
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#define MPC8xxx_PIC_TFRR_OFFSET 0x10F0
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#define PCI1_BASE_ADDR (CFG_IMMR + MPC85xx_PCI1_OFFSET)
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#endif /*__IMMAP_85xx__*/
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