216 lines
5.0 KiB
C
216 lines
5.0 KiB
C
/*
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* imx-iomux-v3.c - i.MX iomux-v3 pinctrl support
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*
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* Copyright (c) 2013 Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <of.h>
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#include <pinctrl.h>
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#include <malloc.h>
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#include <mach/iomux-v3.h>
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struct imx_iomux_v3 {
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void __iomem *base;
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struct pinctrl_device pinctrl;
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};
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static void __iomem *iomuxv3_base;
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static struct device_d *iomuxv3_dev;
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static void imx_iomuxv3_setup_single(void __iomem *base, struct device_d *dev,
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u32 mux_reg, u32 conf_reg, u32 input_reg,
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u32 mux_val, u32 conf_val, u32 input_val)
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{
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dev_dbg(dev,
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"mux: 0x%08x -> 0x%04x, conf: 0x%08x -> 0x%04x input: 0x%08x -> 0x%04x\n",
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mux_val, mux_reg, conf_val, conf_reg, input_val, input_reg);
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if (mux_reg)
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writel(mux_val, base + mux_reg);
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if (conf_reg)
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writel(conf_val, base + conf_reg);
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if (input_reg)
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writel(input_val, base + input_reg);
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}
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/*
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* configures a single pad in the iomuxer
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*/
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int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
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{
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u32 mux_reg = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
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u32 mux_val = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
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u32 input_reg = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
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u32 input_val = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
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u32 conf_reg = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
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u32 conf_val = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
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if (!iomuxv3_base)
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return -EINVAL;
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if (conf_val & NO_PAD_CTRL)
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conf_reg = 0;
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imx_iomuxv3_setup_single(iomuxv3_base, iomuxv3_dev,
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mux_reg, conf_reg, input_reg,
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mux_val, conf_val, input_val);
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return 0;
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}
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EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
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int mxc_iomux_v3_setup_multiple_pads(const iomux_v3_cfg_t *pad_list, unsigned count)
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{
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const iomux_v3_cfg_t *p = pad_list;
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int i;
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int ret;
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for (i = 0; i < count; i++) {
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ret = mxc_iomux_v3_setup_pad(*p);
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if (ret)
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return ret;
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p++;
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}
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return 0;
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}
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EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
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/*
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* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
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* 1 u32 CONFIG, so 24 types in total for each pin.
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*/
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#define FSL_PIN_SIZE 24
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#define IMX_DT_NO_PAD_CTL (1 << 31)
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#define IMX_PAD_SION (1 << 30)
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#define IOMUXC_CONFIG_SION (0x1 << 4)
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static int imx_iomux_v3_set_state(struct pinctrl_device *pdev, struct device_node *np)
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{
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struct imx_iomux_v3 *iomux = container_of(pdev, struct imx_iomux_v3, pinctrl);
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const __be32 *list;
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int npins, size, i;
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dev_dbg(iomux->pinctrl.dev, "set state: %s\n", np->full_name);
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list = of_get_property(np, "fsl,pins", &size);
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if (!list)
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return -EINVAL;
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if (!size || size % FSL_PIN_SIZE) {
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dev_err(iomux->pinctrl.dev, "Invalid fsl,pins property\n");
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return -EINVAL;
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}
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npins = size / FSL_PIN_SIZE;
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for (i = 0; i < npins; i++) {
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u32 mux_reg = be32_to_cpu(*list++);
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u32 conf_reg = be32_to_cpu(*list++);
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u32 input_reg = be32_to_cpu(*list++);
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u32 mux_val = be32_to_cpu(*list++);
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u32 input_val = be32_to_cpu(*list++);
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u32 conf_val = be32_to_cpu(*list++);
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if (conf_val & IMX_PAD_SION)
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mux_val |= IOMUXC_CONFIG_SION;
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if (conf_val & IMX_DT_NO_PAD_CTL)
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conf_reg = 0;
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imx_iomuxv3_setup_single(iomux->base, iomux->pinctrl.dev,
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mux_reg, conf_reg, input_reg,
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mux_val, conf_val, input_val);
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}
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return 0;
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}
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static struct pinctrl_ops imx_iomux_v3_ops = {
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.set_state = imx_iomux_v3_set_state,
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};
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static int imx_pinctrl_dt(struct device_d *dev, void __iomem *base)
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{
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struct imx_iomux_v3 *iomux;
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int ret;
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iomux = xzalloc(sizeof(*iomux));
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iomux->base = base;
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iomux->pinctrl.dev = dev;
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iomux->pinctrl.ops = &imx_iomux_v3_ops;
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ret = pinctrl_register(&iomux->pinctrl);
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if (ret)
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free(iomux);
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return ret;
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}
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static int imx_iomux_v3_probe(struct device_d *dev)
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{
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int ret = 0;
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if (iomuxv3_base)
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return -EBUSY;
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iomuxv3_base = dev_request_mem_region(dev, 0);
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iomuxv3_dev = dev;
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if (IS_ENABLED(CONFIG_PINCTRL) && dev->device_node)
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ret = imx_pinctrl_dt(dev, iomuxv3_base);
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return ret;
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}
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static __maybe_unused struct of_device_id imx_iomux_v3_dt_ids[] = {
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{
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.compatible = "fsl,imx25-iomuxc",
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}, {
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.compatible = "fsl,imx35-iomuxc",
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}, {
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.compatible = "fsl,imx51-iomuxc",
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}, {
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.compatible = "fsl,imx53-iomuxc",
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}, {
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.compatible = "fsl,imx6q-iomuxc",
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}, {
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.compatible = "fsl,imx6dl-iomuxc",
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}, {
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/* sentinel */
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}
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};
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static struct driver_d imx_iomux_v3_driver = {
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.name = "imx-iomuxv3",
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.probe = imx_iomux_v3_probe,
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.of_compatible = DRV_OF_COMPAT(imx_iomux_v3_dt_ids),
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};
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static int imx_iomux_v3_init(void)
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{
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return platform_driver_register(&imx_iomux_v3_driver);
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}
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postcore_initcall(imx_iomux_v3_init);
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