194 lines
7.9 KiB
C
194 lines
7.9 KiB
C
/*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MX31_REGS_H
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#define __ASM_ARCH_MX31_REGS_H
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#include <sizes.h>
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#define MX31_IRAM_BASE_ADDR 0x1fffc000
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#define MX31_IRAM_SIZE 0x00004000
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#define MX31_AIPS1_BASE_ADDR 0x43f00000
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#define MX31_AIPS1_SIZE SZ_1M
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#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
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#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
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#define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000)
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#define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000)
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#define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000)
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#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
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#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
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#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
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#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
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#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
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#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
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#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
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#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
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#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
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#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
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#define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000)
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#define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000)
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#define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000)
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#define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000)
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#define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000)
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#define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000)
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#define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000)
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#define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000)
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#define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000)
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#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
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#define MX31_SPBA0_BASE_ADDR 0x50000000
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#define MX31_SPBA0_SIZE SZ_1M
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#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
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#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
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#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
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#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
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#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
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#define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000)
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#define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000)
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#define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000)
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#define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000)
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#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
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#define MX31_AIPS2_BASE_ADDR 0x53f00000
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#define MX31_AIPS2_SIZE SZ_1M
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#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
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#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
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#define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000)
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#define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000)
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#define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000)
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#define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000)
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#define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000)
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#define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000)
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#define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000)
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#define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000)
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#define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000)
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#define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000)
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#define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000)
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#define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000)
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#define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000)
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#define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000)
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#define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000)
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#define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000)
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#define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000)
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#define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000)
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#define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000)
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#define MX31_ROMP_BASE_ADDR 0x60000000
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#define MX31_ROMP_SIZE SZ_1M
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#define MX31_AVIC_BASE_ADDR 0x68000000
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#define MX31_AVIC_SIZE SZ_1M
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#define MX31_IPU_MEM_BASE_ADDR 0x70000000
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#define MX31_CSD0_BASE_ADDR 0x80000000
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#define MX31_CSD1_BASE_ADDR 0x90000000
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#define MX31_CS0_BASE_ADDR 0xa0000000
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#define MX31_CS0_SIZE SZ_128M
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#define MX31_CS1_BASE_ADDR 0xa8000000
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#define MX31_CS1_SIZE SZ_128M
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#define MX31_CS2_BASE_ADDR 0xb0000000
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#define MX31_CS2_SIZE SZ_32M
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#define MX31_CS3_BASE_ADDR 0xb2000000
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#define MX31_CS3_SIZE SZ_32M
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#define MX31_CS4_BASE_ADDR 0xb4000000
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#define MX31_CS4_SIZE SZ_32M
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#define MX31_CS5_BASE_ADDR 0xb6000000
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#define MX31_CS5_SIZE SZ_32M
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#define MX31_X_MEMC_BASE_ADDR 0xb8000000
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#define MX31_X_MEMC_SIZE SZ_64K
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#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
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#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
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#define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000)
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#define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000)
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#define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000)
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#define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR
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#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10)
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#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs))
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#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
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#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
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#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
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/*
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* Clock Controller Module (CCM)
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*/
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#define MX31_CCM_CCMR 0x00
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#define MX31_CCM_PDR0 0x04
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#define MX31_CCM_PDR1 0x08
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#define MX31_CCM_RCSR 0x0c
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#define MX31_CCM_MPCTL 0x10
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#define MX31_CCM_UPCTL 0x14
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#define MX31_CCM_SPCTL 0x18
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#define MX31_CCM_COSR 0x1C
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#define MX31_CCMR_MDS (1 << 7)
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#define MX31_CCMR_SBYCS (1 << 4)
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#define MX31_CCMR_MPE (1 << 3)
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#define MX31_CCMR_PRCS_MASK (3 << 1)
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#define MX31_CCMR_FPM (1 << 1)
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#define MX31_CCMR_CKIH (2 << 1)
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#define MX31_RCSR_NFMS (1 << 30)
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#define MX31_PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
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#define MX31_PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
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#define MX31_PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
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#define MX31_PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
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#define MX31_PDR0_IPG_PODF(x) (((x) & 0x3) << 6)
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#define MX31_PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
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#define MX31_PDR0_MCU_PODF(x) ((x) & 0x7)
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#define MX31_IOMUXC_GPR (MX31_IOMUXC_BASE_ADDR + 0x8)
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#define MX31_IOMUXC_SW_MUX_CTL(x) (MX31_IOMUXC_BASE_ADDR + 0xc + (x) * 4)
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#define MX31_IOMUXC_SW_PAD_CTL(x) (MX31_IOMUXC_BASE_ADDR + 0x154 + (x) * 4)
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/*
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* Signal Multiplexing (IOMUX)
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*/
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/* bits in the SW_MUX_CTL registers */
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#define MX31_MUX_CTL_OUT_GPIO_DR (0 << 4)
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#define MX31_MUX_CTL_OUT_FUNC (1 << 4)
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#define MX31_MUX_CTL_OUT_ALT1 (2 << 4)
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#define MX31_MUX_CTL_OUT_ALT2 (3 << 4)
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#define MX31_MUX_CTL_OUT_ALT3 (4 << 4)
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#define MX31_MUX_CTL_OUT_ALT4 (5 << 4)
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#define MX31_MUX_CTL_OUT_ALT5 (6 << 4)
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#define MX31_MUX_CTL_OUT_ALT6 (7 << 4)
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#define MX31_MUX_CTL_IN_NONE (0 << 0)
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#define MX31_MUX_CTL_IN_GPIO (1 << 0)
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#define MX31_MUX_CTL_IN_FUNC (2 << 0)
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#define MX31_MUX_CTL_IN_ALT1 (4 << 0)
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#define MX31_MUX_CTL_IN_ALT2 (8 << 0)
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#define MX31_MUX_CTL_FUNC (MX31_MUX_CTL_OUT_FUNC | MX31_MUX_CTL_IN_FUNC)
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#define MX31_MUX_CTL_ALT1 (MX31_MUX_CTL_OUT_ALT1 | MX31_MUX_CTL_IN_ALT1)
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#define MX31_MUX_CTL_ALT2 (MX31_MUX_CTL_OUT_ALT2 | MX31_MUX_CTL_IN_ALT2)
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#define MX31_MUX_CTL_GPIO (MX31_MUX_CTL_OUT_GPIO_DR | MX31_MUX_CTL_IN_GPIO)
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#endif /* __ASM_ARCH_MX31_REGS_H */
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