169 lines
6.5 KiB
C
169 lines
6.5 KiB
C
/*
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* (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MX35_REGS_H
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#define __ASM_ARCH_MX35_REGS_H
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#include <sizes.h>
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#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
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#define MX35_IRAM_SIZE SZ_128K
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#define MX35_L2CC_BASE_ADDR 0x30000000
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#define MX35_L2CC_SIZE SZ_1M
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#define MX35_AIPS1_BASE_ADDR 0x43f00000
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#define MX35_AIPS1_SIZE SZ_1M
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#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
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#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
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#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
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#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
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#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
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#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
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#define MX35_I2C1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
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#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
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#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
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#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
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#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
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#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
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#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
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#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
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#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
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#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
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#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
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#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
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#define MX35_SPBA0_BASE_ADDR 0x50000000
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#define MX35_SPBA0_SIZE SZ_1M
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#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
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#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
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#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
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#define MX35_ATA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
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#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
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#define MX35_FEC_BASE_ADDR 0x50038000
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#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
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#define MX35_AIPS2_BASE_ADDR 0x53f00000
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#define MX35_AIPS2_SIZE SZ_1M
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#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
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#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
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#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
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#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
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#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
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#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
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#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
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#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
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#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
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#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
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#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
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#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
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#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
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#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
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#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
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#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
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#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
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#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
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#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
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#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
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#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
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#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
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#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
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#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
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/*
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* The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
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* HS. When host support was implemented only a preliminary document was
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* available, which told 0x400. This works fine.
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*/
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#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
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#define MX35_ROMP_BASE_ADDR 0x60000000
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#define MX35_ROMP_SIZE SZ_1M
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#define MX35_AVIC_BASE_ADDR 0x68000000
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#define MX35_AVIC_SIZE SZ_1M
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/*
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* Memory regions and CS
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*/
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#define MX35_IPU_MEM_BASE_ADDR 0x70000000
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#define MX35_CSD0_BASE_ADDR 0x80000000
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#define MX35_CSD1_BASE_ADDR 0x90000000
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#define MX35_CS0_BASE_ADDR 0xa0000000
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#define MX35_CS1_BASE_ADDR 0xa8000000
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#define MX35_CS2_BASE_ADDR 0xb0000000
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#define MX35_CS3_BASE_ADDR 0xb2000000
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#define MX35_CS4_BASE_ADDR 0xb4000000
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#define MX35_CS4_SIZE SZ_32M
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#define MX35_CS5_BASE_ADDR 0xb6000000
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#define MX35_CS5_SIZE SZ_32M
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define MX35_X_MEMC_BASE_ADDR 0xb8000000
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#define MX35_X_MEMC_SIZE SZ_64K
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#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
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#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
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#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
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#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
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#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
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#define MX35_NFC_BASE_ADDR 0xbb000000
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#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
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/*
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* Clock Controller Module (CCM)
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*/
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#define MX35_CCM_CCMR 0x00
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#define MX35_CCM_PDR0 0x04
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#define MX35_CCM_PDR1 0x08
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#define MX35_CCM_PDR2 0x0C
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#define MX35_CCM_PDR3 0x10
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#define MX35_CCM_PDR4 0x14
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#define MX35_CCM_RCSR 0x18
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#define MX35_CCM_MPCTL 0x1C
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#define MX35_CCM_PPCTL 0x20
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#define MX35_CCM_ACMR 0x24
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#define MX35_CCM_COSR 0x28
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#define MX35_CCM_CGR0 0x2C
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#define MX35_CCM_CGR1 0x30
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#define MX35_CCM_CGR2 0x34
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#define MX35_CCM_CGR3 0x38
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#define MX35_CCM_CGR0_CSPI1_SHIFT 10
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#define MX35_CCM_CGR1_FEC_SHIFT 0
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#define MX35_CCM_CGR1_I2C1_SHIFT 10
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#define MX35_CCM_CGR1_SDHC1_SHIFT 26
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#define MX35_CCM_CGR2_USB_SHIFT 22
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#define MX35_CCM_RCSR_MEM_CTRL_SHIFT 25
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#define MX35_CCM_RCSR_MEM_TYPE_SHIFT 23
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#define MX35_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
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#define MX35_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
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#define MX35_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
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#define MX35_PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
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#define MX35_PDR0_AUTO_CON (1 << 0)
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#define MX35_PDR0_PER_SEL (1 << 26)
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#endif /* __ASM_ARCH_MX35_REGS_H */
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