139 lines
4.9 KiB
C
139 lines
4.9 KiB
C
/*
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* (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MX25_REGS_H
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#define __ASM_ARCH_MX25_REGS_H
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#define MX25_AIPS1_BASE_ADDR 0x43f00000
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#define MX25_AIPS1_SIZE SZ_1M
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#define MX25_AIPS2_BASE_ADDR 0x53f00000
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#define MX25_AIPS2_SIZE SZ_1M
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#define MX25_AVIC_BASE_ADDR 0x68000000
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#define MX25_AVIC_SIZE SZ_1M
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#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
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#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
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#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
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#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
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#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
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#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
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#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
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#define MX25_CCM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
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#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
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#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
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#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
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#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
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#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
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#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
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#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
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#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
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#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
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#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
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#define MX25_UART1_BASE_ADDR 0x43f90000
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#define MX25_UART2_BASE_ADDR 0x43f94000
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#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
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#define MX25_UART3_BASE_ADDR 0x5000c000
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#define MX25_UART4_BASE_ADDR 0x50008000
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#define MX25_UART5_BASE_ADDR 0x5002c000
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#define MX25_CSPI3_BASE_ADDR 0x50004000
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#define MX25_CSPI2_BASE_ADDR 0x50010000
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#define MX25_FEC_BASE_ADDR 0x50038000
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#define MX25_SSI2_BASE_ADDR 0x50014000
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#define MX25_SSI1_BASE_ADDR 0x50034000
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#define MX25_NFC_BASE_ADDR 0xbb000000
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#define MX25_IIM_BASE_ADDR 0x53ff0000
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#define MX25_DRYICE_BASE_ADDR 0x53ffc000
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#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
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#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
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#define MX25_LCDC_BASE_ADDR 0x53fbc000
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#define MX25_KPP_BASE_ADDR 0x43fa8000
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#define MX25_SDMA_BASE_ADDR 0x53fd4000
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#define MX25_USB_BASE_ADDR 0x53ff4000
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#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
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/*
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* The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
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* for the host controller. Early documentation drafts specified 0x400 and
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* Freescale internal sources confirm only the latter value to work.
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*/
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#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
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#define MX25_CSI_BASE_ADDR 0x53ff8000
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#define MX25_IRAM_BASE_ADDR 0x78000000 /* internal ram */
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#define MX25_IRAM_SIZE SZ_128K
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/*
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* Clock Controller Module (CCM)
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*/
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#define MX25_CCM_MPCTL 0x00
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#define MX25_CCM_UPCTL 0x04
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#define MX25_CCM_CCTL 0x08
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#define MX25_CCM_CGCR0 0x0C
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#define MX25_CCM_CGCR1 0x10
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#define MX25_CCM_CGCR2 0x14
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#define MX25_CCM_PCDR0 0x18
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#define MX25_CCM_PCDR1 0x1C
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#define MX25_CCM_PCDR2 0x20
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#define MX25_CCM_PCDR3 0x24
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#define MX25_CCM_RCSR 0x28
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#define MX25_CCM_CRDR 0x2C
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#define MX25_CCM_DCVR0 0x30
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#define MX25_CCM_DCVR1 0x34
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#define MX25_CCM_DCVR2 0x38
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#define MX25_CCM_DCVR3 0x3c
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#define MX25_CCM_LTR0 0x40
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#define MX25_CCM_LTR1 0x44
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#define MX25_CCM_LTR2 0x48
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#define MX25_CCM_LTR3 0x4c
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#define MX25_PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9)
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#define MX25_PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12)
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#define MX25_PDR0_CON_MUX_DIV(x) (((x) & 0xf) << 16)
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#define MX25_PDR0_HSP_PODF(x) (((x) & 0x3) << 20)
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#define MX25_PDR0_AUTO_CON (1 << 0)
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#define MX25_PDR0_PER_SEL (1 << 26)
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#define MX25_CCM_RCSR_MEM_CTRL_SHIFT 30
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#define MX25_CCM_RCSR_MEM_TYPE_SHIFT 28
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/*
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* Adresses and ranges of the external chip select lines
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*/
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#define MX25_CS0_BASE_ADDR 0xA0000000
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#define MX25_CS0_SIZE SZ_128M
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#define MX25_CS1_BASE_ADDR 0xA8000000
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#define MX25_CS1_SIZE SZ_128M
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#define MX25_CS2_BASE_ADDR 0xB0000000
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#define MX25_CS2_SIZE SZ_32M
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#define MX25_CS3_BASE_ADDR 0xB2000000
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#define MX25_CS3_SIZE SZ_32M
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#define MX25_CS4_BASE_ADDR 0xB4000000
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#define MX25_CS4_SIZE SZ_32M
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#define MX25_CS5_BASE_ADDR 0xB6000000
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#define MX25_CS5_SIZE SZ_32M
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#define MX25_CSD0_BASE_ADDR 0x80000000
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#define MX25_CSD1_BASE_ADDR 0x90000000
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#define MX25_ESDCTL_BASE_ADDR 0xb8001000
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#define MX25_WEIM_BASE_ADDR 0xb8002000
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#endif /* __ASM_ARCH_MX25_REGS_H */
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