326 lines
7.4 KiB
Plaintext
326 lines
7.4 KiB
Plaintext
/dts-v1/;
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#include "imx6dl.dtsi"
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#include <arm/imx6dl.dtsi>
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/ {
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model = "ELTEC HiPerCam";
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compatible = "eltec,hipercam-rev01", "fsl,imx6dl";
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memory {
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reg = <0x10000000 0x10000000>;
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};
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chosen {
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stdout-path = &uart1;
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environment@0 {
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compatible = "barebox,environment";
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device-path = &environment_nor0;
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};
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};
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};
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&ecspi1 {
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status = "okay";
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fsl,spi-num-chipselects = <2>;
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pinctrl-names = "default";
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cs-gpios = <&gpio2 30 0 &gpio3 19 0>;
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pinctrl-0 = <&pinctrl_ecspi1>;
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norflash0: s25fl129p1@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "st,s25fl129p1";
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spi-max-frequency = <20000000>;
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reg = <0x0>;
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partition@0 {
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label = "barebox";
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reg = <0x0 0xc0000>;
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};
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environment_nor0: partition@1 {
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label = "bareboxenv";
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reg = <0xc0000 0x8000>;
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};
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partition@2 {
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label = "persistent";
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reg = <0x100000 0xf00000>;
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};
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};
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norflash1: s25fl129p1@1 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "st,s25fl129p1";
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spi-max-frequency = <20000000>;
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reg = <0x1>;
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partition@0 {
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label = "Linux";
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reg = <0x0 0x1000000>;
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};
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};
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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};
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&pcie {
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status = "okay";
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reset-gpio = <&gpio7 12 0x0>;
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};
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&usdhc3 {
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bus-width = <0x4>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc3>;
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cd-gpios = <&gpio2 2 0>;
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wp-gpios = <&gpio2 1 0>;
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no-1-8-v;
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};
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&i2c2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x20>;
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eeprom@0x52 {
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compatible = "amtel,24c04";
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reg = <0x52>;
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pagesize = <0x10>;
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};
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pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x8>;
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regulators {
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sw1ab {
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regulator-min-microvolt = <0x493e0>;
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regulator-max-microvolt = <0x1c9c38>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <0x186a>;
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};
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sw1c {
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regulator-min-microvolt = <0x493e0>;
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regulator-max-microvolt = <0x1c9c38>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <0x186a>;
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};
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sw2 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3a {
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regulator-min-microvolt = <0x61a80>;
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regulator-max-microvolt = <0x1e22d8>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3b {
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regulator-min-microvolt = <0x61a80>;
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regulator-max-microvolt = <0x1e22d8>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw4 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x325aa0>;
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};
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swbst {
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regulator-min-microvolt = <0x4c4b40>;
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regulator-max-microvolt = <0x4e9530>;
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};
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vsnvs {
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regulator-min-microvolt = <0xf4240>;
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regulator-max-microvolt = <0x2dc6c0>;
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regulator-boot-on;
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regulator-always-on;
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};
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vrefddr {
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regulator-boot-on;
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regulator-always-on;
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};
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vgen1 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x17a6b0>;
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};
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vgen2 {
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regulator-min-microvolt = <0xc3500>;
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regulator-max-microvolt = <0x17a6b0>;
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};
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vgen3 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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};
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vgen4 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-always-on;
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};
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vgen5 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-always-on;
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};
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vgen6 {
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regulator-min-microvolt = <0x1b7740>;
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regulator-max-microvolt = <0x325aa0>;
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regulator-always-on;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <0x1d>;
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mt9p031@48 {
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compatible = "aptina,mt9p031";
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reg = <0x48>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_cam>;
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csi_id = <0x0>;
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clocks = <&clks 201>;
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clock-names = "csi_mclk";
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rst-gpios = <&gpio5 22 0>;
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data-enable-gpios = <&gpio5 20 0x0>;
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mclk = <12000000>;
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mclk_source = <0>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx6dl-eltec-hipercam {
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pinctrl_ecspi1: ecspi1 {
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fsl,pins = <MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
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MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
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MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
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MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
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MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
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>;
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};
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pinctrl_i2c1: i2c1 {
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fsl,pins = <MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
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MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
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>;
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};
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pinctrl_i2c2: i2c2 {
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fsl,pins = <MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c3: i2c3 {
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fsl,pins = <MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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>;
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};
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pinctrl_pwm1: pwm1 {
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fsl,pins = <MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1>;
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};
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pinctrl_uart1: uart1 {
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fsl,pins = <MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
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MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
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>;
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};
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pinctrl_usdhc3: usdhc3 {
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fsl,pins = <MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
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>;
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};
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pinctrl_hog: hog {
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fsl,pins = <MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
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MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
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MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
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MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
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MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
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MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
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MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
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MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
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MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
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MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
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MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
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MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
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MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
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MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
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MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
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MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
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MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
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MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
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MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
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MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
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MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
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MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x80000000
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MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
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MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
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MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
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>;
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};
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pinctrl_cam: cam {
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fsl,pins = <MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000
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MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
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MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
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MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
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MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
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MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
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MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
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MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
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MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
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MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
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MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
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MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000
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MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
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MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
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MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
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>;
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};
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};
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};
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