93 lines
2.0 KiB
Plaintext
93 lines
2.0 KiB
Plaintext
/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <arm/imx6sx-sdb.dts>
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#include "imx6sx.dtsi"
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/ {
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chosen {
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environment@0 {
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compatible = "barebox,environment";
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device-path = &usdhc4, "partname:barebox-environment";
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};
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};
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};
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&fec1 {
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phy-handle = <&phy1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: phy@1 {
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reg = <1>;
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};
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phy2: phy@2 {
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reg = <2>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rgmii";
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status = "okay";
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phy-handle = <&phy2>;
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};
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&ocotp {
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barebox,provide-mac-address = <&fec1 0x620 &fec2 0x632>;
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};
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&usdhc4 {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "barebox-environment";
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reg = <0x80000 0x20000>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx6x-sdb {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x17059 /* PERI_3V3 */
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MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x17059 /* ENET PHY Power */
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MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x17059 /* AR8031 PHY Reset. */
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MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x17059 /* Phy 25M Clock */
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b1
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MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
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MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
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MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
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MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
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MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
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MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
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MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
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MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
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MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
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MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
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MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
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>;
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};
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};
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};
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