571 lines
16 KiB
C
571 lines
16 KiB
C
/*
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* Altera TSE Network driver
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*
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* Copyright (C) 2008 Altera Corporation.
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (C) 2011 Franck JULLIEN, <elec4fun@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <dma.h>
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#include <net.h>
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#include <init.h>
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#include <clock.h>
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#include <linux/mii.h>
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#include <linux/phy.h>
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#include <linux/err.h>
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#include <io.h>
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#include <asm/dma-mapping.h>
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#include "altera_tse.h"
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/* This is a generic routine that the SGDMA mode-specific routines
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* call to populate a descriptor.
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* arg1 :pointer to first SGDMA descriptor.
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* arg2 :pointer to next SGDMA descriptor.
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* arg3 :Address to where data to be written.
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* arg4 :Address from where data to be read.
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* arg5 :no of byte to transaction.
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* arg6 :variable indicating to generate start of packet or not
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* arg7 :read fixed
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* arg8 :write fixed
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* arg9 :read burst
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* arg10 :write burst
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* arg11 :atlantic_channel number
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*/
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static void alt_sgdma_construct_descriptor_burst(
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struct alt_sgdma_descriptor *desc,
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struct alt_sgdma_descriptor *next,
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uint32_t *read_addr,
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uint32_t *write_addr,
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uint16_t length_or_eop,
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uint8_t generate_eop,
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uint8_t read_fixed,
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uint8_t write_fixed_or_sop,
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uint8_t read_burst,
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uint8_t write_burst,
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uint8_t atlantic_channel)
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{
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uint32_t temp;
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/*
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* Mark the "next" descriptor as "not" owned by hardware. This prevents
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* The SGDMA controller from continuing to process the chain. This is
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* done as a single IO write to bypass cache, without flushing
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* the entire descriptor, since only the 8-bit descriptor status must
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* be flushed.
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*/
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if (!next)
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printf("Next descriptor not defined!!\n");
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temp = readb(&next->descriptor_control);
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writeb(temp & ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK,
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&next->descriptor_control);
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writel((uint32_t)read_addr, &desc->source);
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writel((uint32_t)write_addr, &desc->destination);
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writel((uint32_t)next, &desc->next);
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writel(0, &desc->source_pad);
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writel(0, &desc->destination_pad);
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writel(0, &desc->next_pad);
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writew(length_or_eop, &desc->bytes_to_transfer);
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writew(0, &desc->actual_bytes_transferred);
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writeb(0, &desc->descriptor_status);
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/* SGDMA burst not currently supported */
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writeb(0, &desc->read_burst);
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writeb(0, &desc->write_burst);
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/*
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* Set the descriptor control block as follows:
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* - Set "owned by hardware" bit
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* - Optionally set "generate EOP" bit
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* - Optionally set the "read from fixed address" bit
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* - Optionally set the "write to fixed address bit (which serves
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* serves as a "generate SOP" control bit in memory-to-stream mode).
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* - Set the 4-bit atlantic channel, if specified
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*
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* Note this step is performed after all other descriptor information
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* has been filled out so that, if the controller already happens to be
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* pointing at this descriptor, it will not run (via the "owned by
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* hardware" bit) until all other descriptor has been set up.
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*/
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writeb((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) |
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(generate_eop ? ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0) |
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(read_fixed ? ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0) |
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(write_fixed_or_sop ? ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0) |
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(atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0),
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&desc->descriptor_control);
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}
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static int alt_sgdma_do_sync_transfer(struct alt_sgdma_registers *dev,
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struct alt_sgdma_descriptor *desc)
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{
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uint32_t temp;
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uint64_t start;
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uint64_t tout;
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/* Wait for any pending transfers to complete */
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tout = ALT_TSE_SGDMA_BUSY_WATCHDOG_TOUT * MSECOND;
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start = get_time_ns();
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while (readl(&dev->status) & ALT_SGDMA_STATUS_BUSY_MSK) {
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if (is_timeout(start, tout)) {
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debug("Timeout waiting sgdma in do sync!\n");
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break;
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}
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}
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/*
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* Clear any (previous) status register information
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* that might occlude our error checking later.
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*/
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writel(0xFF, &dev->status);
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/* Point the controller at the descriptor */
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writel((uint32_t)desc, &dev->next_descriptor_pointer);
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debug("next desc in sgdma 0x%x\n", (uint32_t)dev->next_descriptor_pointer);
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/*
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* Set up SGDMA controller to:
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* - Disable interrupt generation
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* - Run once a valid descriptor is written to controller
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* - Stop on an error with any particular descriptor
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*/
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writel(ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK,
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&dev->control);
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/* Wait for the descriptor (chain) to complete */
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debug("wait for sgdma....");
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start = get_time_ns();
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while (readl(&dev->status) & ALT_SGDMA_STATUS_BUSY_MSK) {
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if (is_timeout(start, tout)) {
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debug("Timeout waiting sgdma in do sync!\n");
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break;
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}
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}
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debug("done\n");
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/* Clear Run */
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temp = readl(&dev->control);
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writel(temp & ~ALT_SGDMA_CONTROL_RUN_MSK, &dev->control);
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/* Get & clear status register contents */
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debug("tx sgdma status = 0x%x", readl(&dev->status));
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writel(0xFF, &dev->status);
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return 0;
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}
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static int alt_sgdma_do_async_transfer(struct alt_sgdma_registers *dev,
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struct alt_sgdma_descriptor *desc)
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{
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uint64_t start;
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uint64_t tout;
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/* Wait for any pending transfers to complete */
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tout = ALT_TSE_SGDMA_BUSY_WATCHDOG_TOUT * MSECOND;
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start = get_time_ns();
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while (readl(&dev->status) & ALT_SGDMA_STATUS_BUSY_MSK) {
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if (is_timeout(start, tout)) {
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debug("Timeout waiting sgdma in do async!\n");
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break;
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}
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}
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/*
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* Clear any (previous) status register information
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* that might occlude our error checking later.
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*/
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writel(0xFF, &dev->status);
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/* Point the controller at the descriptor */
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writel((uint32_t)desc, &dev->next_descriptor_pointer);
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/*
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* Set up SGDMA controller to:
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* - Disable interrupt generation
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* - Run once a valid descriptor is written to controller
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* - Stop on an error with any particular descriptor
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*/
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writel(ALT_SGDMA_CONTROL_RUN_MSK | ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK,
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&dev->control);
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return 0;
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}
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static int tse_get_ethaddr(struct eth_device *edev, unsigned char *m)
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{
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struct altera_tse_priv *priv = edev->priv;
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struct alt_tse_mac *mac_dev = priv->tse_regs;
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m[5] = (readl(&mac_dev->mac_addr_1) >> 8) && 0xFF;
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m[4] = (readl(&mac_dev->mac_addr_1)) && 0xFF;
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m[3] = (readl(&mac_dev->mac_addr_0) >> 24) && 0xFF;
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m[2] = (readl(&mac_dev->mac_addr_0) >> 16) && 0xFF;
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m[1] = (readl(&mac_dev->mac_addr_0) >> 8) && 0xFF;
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m[0] = (readl(&mac_dev->mac_addr_0)) && 0xFF;
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return 0;
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}
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static int tse_set_ethaddr(struct eth_device *edev, unsigned char *m)
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{
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struct altera_tse_priv *priv = edev->priv;
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struct alt_tse_mac *mac_dev = priv->tse_regs;
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debug("Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n",
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m[0], m[1], m[2], m[3], m[4], m[5]);
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writel(m[3] << 24 | m[2] << 16 | m[1] << 8 | m[0], &mac_dev->mac_addr_0);
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writel((m[5] << 8 | m[4]) & 0xFFFF, &mac_dev->mac_addr_1);
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return 0;
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}
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static int tse_phy_read(struct mii_bus *bus, int phy_addr, int reg)
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{
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struct altera_tse_priv *priv = bus->priv;
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struct alt_tse_mac *mac_dev = priv->tse_regs;
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uint32_t *mdio_regs;
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writel(phy_addr, &mac_dev->mdio_phy1_addr);
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mdio_regs = (uint32_t *)&mac_dev->mdio_phy1;
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return readl(&mdio_regs[reg]) & 0xFFFF;
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}
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static int tse_phy_write(struct mii_bus *bus, int phy_addr, int reg, u16 val)
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{
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struct altera_tse_priv *priv = bus->priv;
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struct alt_tse_mac *mac_dev = priv->tse_regs;
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uint32_t *mdio_regs;
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writel(phy_addr, &mac_dev->mdio_phy1_addr);
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mdio_regs = (uint32_t *)&mac_dev->mdio_phy1;
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writel((uint32_t)val, &mdio_regs[reg]);
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return 0;
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}
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static void tse_reset(struct eth_device *edev)
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{
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/* stop sgdmas, disable tse receive */
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struct altera_tse_priv *priv = edev->priv;
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struct alt_tse_mac *mac_dev = priv->tse_regs;
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struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx_regs;
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struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx_regs;
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
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uint64_t start;
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uint64_t tout;
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tout = ALT_TSE_SGDMA_BUSY_WATCHDOG_TOUT * MSECOND;
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/* clear rx desc & wait for sgdma to complete */
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writeb(0, &rx_desc->descriptor_control);
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writel(0, &rx_sgdma->control);
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &rx_sgdma->control);
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &rx_sgdma->control);
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mdelay(100);
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start = get_time_ns();
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while (readl(&rx_sgdma->status) & ALT_SGDMA_STATUS_BUSY_MSK) {
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if (is_timeout(start, tout)) {
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printf("Timeout waiting for rx sgdma!\n");
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &rx_sgdma->control);
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &rx_sgdma->control);
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break;
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}
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}
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/* clear tx desc & wait for sgdma to complete */
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writeb(0, &tx_desc->descriptor_control);
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writel(0, &tx_sgdma->control);
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &tx_sgdma->control);
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &tx_sgdma->control);
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mdelay(100);
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start = get_time_ns();
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while (readl(&tx_sgdma->status) & ALT_SGDMA_STATUS_BUSY_MSK) {
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if (is_timeout(start, tout)) {
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printf("Timeout waiting for tx sgdma!\n");
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &tx_sgdma->control);
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writel(ALT_SGDMA_CONTROL_SOFTWARERESET_MSK, &tx_sgdma->control);
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break;
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}
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}
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/* reset the mac */
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writel(ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK |
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ALTERA_TSE_CMD_SW_RESET_MSK, &mac_dev->command_config);
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start = get_time_ns();
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tout = ALT_TSE_SW_RESET_WATCHDOG_TOUT * MSECOND;
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while (readl(&mac_dev->command_config) & ALTERA_TSE_CMD_SW_RESET_MSK) {
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if (is_timeout(start, tout)) {
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printf("TSEMAC SW reset bit never cleared!\n");
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break;
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}
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}
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}
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static int tse_eth_open(struct eth_device *edev)
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{
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struct altera_tse_priv *priv = edev->priv;
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int ret;
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ret = phy_device_connect(edev, priv->miibus, priv->phy_addr, NULL, 0,
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PHY_INTERFACE_MODE_NA);
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if (ret)
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return ret;
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return 0;
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}
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static int tse_eth_send(struct eth_device *edev, void *packet, int length)
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{
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struct altera_tse_priv *priv = edev->priv;
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struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx_regs;
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struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
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struct alt_sgdma_descriptor *tx_desc_cur = tx_desc;
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flush_dcache_range((uint32_t)packet, (uint32_t)packet + length);
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alt_sgdma_construct_descriptor_burst(
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(struct alt_sgdma_descriptor *)&tx_desc[0],
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(struct alt_sgdma_descriptor *)&tx_desc[1],
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(uint32_t *)packet, /* read addr */
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(uint32_t *)0, /* */
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length, /* length or EOP ,will change for each tx */
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0x1, /* gen eop */
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0x0, /* read fixed */
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0x1, /* write fixed or sop */
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0x0, /* read burst */
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0x0, /* write burst */
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0x0 /* channel */
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);
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alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur);
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return 0;
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}
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static void tse_eth_halt(struct eth_device *edev)
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{
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struct altera_tse_priv *priv = edev->priv;
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struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx_regs;
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struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx_regs;
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writel(0, &rx_sgdma->control); /* Stop the controller and reset settings */
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writel(0, &tx_sgdma->control); /* Stop the controller and reset settings */
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}
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static int tse_eth_rx(struct eth_device *edev)
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{
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uint16_t packet_length = 0;
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struct altera_tse_priv *priv = edev->priv;
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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struct alt_sgdma_descriptor *rx_desc_cur = rx_desc;
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struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx_regs;
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if (rx_desc_cur->descriptor_status &
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ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) {
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packet_length = rx_desc->actual_bytes_transferred;
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net_receive(edev, NetRxPackets[0], packet_length);
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/* Clear Run */
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rx_sgdma->control = (rx_sgdma->control & (~ALT_SGDMA_CONTROL_RUN_MSK));
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/* start descriptor again */
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flush_dcache_range((uint32_t)(NetRxPackets[0]), (uint32_t)(NetRxPackets[0]) + PKTSIZE);
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alt_sgdma_construct_descriptor_burst(
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(struct alt_sgdma_descriptor *)&rx_desc[0],
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(struct alt_sgdma_descriptor *)&rx_desc[1],
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(uint32_t)0x0, /* read addr */
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(uint32_t *)NetRxPackets[0], /* */
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0x0, /* length or EOP */
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0x0, /* gen eop */
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0x0, /* read fixed */
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0x0, /* write fixed or sop */
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0x0, /* read burst */
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0x0, /* write burst */
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0x0 /* channel */
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);
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/* setup the sgdma */
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alt_sgdma_do_async_transfer(priv->sgdma_rx_regs, rx_desc);
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}
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return 0;
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}
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static int tse_init_dev(struct eth_device *edev)
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{
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struct altera_tse_priv *priv = edev->priv;
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struct alt_tse_mac *mac_dev = priv->tse_regs;
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struct alt_sgdma_descriptor *tx_desc = priv->tx_desc;
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struct alt_sgdma_descriptor *rx_desc = priv->rx_desc;
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struct alt_sgdma_descriptor *rx_desc_cur;
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rx_desc_cur = rx_desc;
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tse_reset(edev);
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/* need to create sgdma */
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alt_sgdma_construct_descriptor_burst(
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(struct alt_sgdma_descriptor *)&tx_desc[0],
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(struct alt_sgdma_descriptor *)&tx_desc[1],
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(uint32_t *)NULL, /* read addr */
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(uint32_t *)0, /* */
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0, /* length or EOP ,will change for each tx */
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0x1, /* gen eop */
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0x0, /* read fixed */
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0x1, /* write fixed or sop */
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0x0, /* read burst */
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0x0, /* write burst */
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0x0 /* channel */
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);
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flush_dcache_range((uint32_t)(NetRxPackets[0]), (uint32_t)(NetRxPackets[0]) + PKTSIZE);
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alt_sgdma_construct_descriptor_burst(
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(struct alt_sgdma_descriptor *)&rx_desc[0],
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(struct alt_sgdma_descriptor *)&rx_desc[1],
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(uint32_t)0x0, /* read addr */
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(uint32_t *)NetRxPackets[0], /* */
|
|
0x0, /* length or EOP */
|
|
0x0, /* gen eop */
|
|
0x0, /* read fixed */
|
|
0x0, /* write fixed or sop */
|
|
0x0, /* read burst */
|
|
0x0, /* write burst */
|
|
0x0 /* channel */
|
|
);
|
|
|
|
/* start rx async transfer */
|
|
alt_sgdma_do_async_transfer(priv->sgdma_rx_regs, rx_desc_cur);
|
|
|
|
/* Initialize MAC registers */
|
|
writel(PKTSIZE, &mac_dev->max_frame_length);
|
|
|
|
/* NO Shift */
|
|
writel(0, &mac_dev->rx_cmd_stat);
|
|
writel(0, &mac_dev->tx_cmd_stat);
|
|
|
|
/* enable MAC */
|
|
writel(ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK, &mac_dev->command_config);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tse_probe(struct device_d *dev)
|
|
{
|
|
struct altera_tse_priv *priv;
|
|
struct mii_bus *miibus;
|
|
struct eth_device *edev;
|
|
struct alt_sgdma_descriptor *rx_desc;
|
|
struct alt_sgdma_descriptor *tx_desc;
|
|
#ifndef CONFIG_TSE_USE_DEDICATED_DESC_MEM
|
|
uint32_t dma_handle;
|
|
#endif
|
|
edev = xzalloc(sizeof(struct eth_device));
|
|
priv = xzalloc(sizeof(struct altera_tse_priv));
|
|
miibus = xzalloc(sizeof(struct mii_bus));
|
|
|
|
edev->priv = priv;
|
|
|
|
edev->init = tse_init_dev;
|
|
edev->open = tse_eth_open;
|
|
edev->send = tse_eth_send;
|
|
edev->recv = tse_eth_rx;
|
|
edev->halt = tse_eth_halt;
|
|
edev->get_ethaddr = tse_get_ethaddr;
|
|
edev->set_ethaddr = tse_set_ethaddr;
|
|
edev->parent = dev;
|
|
|
|
#ifdef CONFIG_TSE_USE_DEDICATED_DESC_MEM
|
|
tx_desc = dev_request_mem_region(dev, 3);
|
|
if (IS_ERR(tx_desc))
|
|
return PTR_ERR(tx_desc);
|
|
rx_desc = tx_desc + 2;
|
|
#else
|
|
tx_desc = dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), (dma_addr_t *)&dma_handle);
|
|
rx_desc = tx_desc + 2;
|
|
|
|
if (!tx_desc) {
|
|
free(edev);
|
|
free(miibus);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1));
|
|
memset(tx_desc, 0, (sizeof *tx_desc) * 2);
|
|
|
|
priv->tse_regs = dev_request_mem_region(dev, 0);
|
|
if (IS_ERR(priv->tse_regs))
|
|
return PTR_ERR(priv->tse_regs);
|
|
priv->sgdma_rx_regs = dev_request_mem_region(dev, 1);
|
|
if (IS_ERR(priv->sgdma_rx_regs))
|
|
return PTR_ERR(priv->sgdma_rx_regs);
|
|
priv->sgdma_tx_regs = dev_request_mem_region(dev, 2);
|
|
if (IS_ERR(priv->sgdma_tx_regs))
|
|
return PTR_ERR(priv->sgdma_tx_regs);
|
|
priv->rx_desc = rx_desc;
|
|
priv->tx_desc = tx_desc;
|
|
|
|
priv->miibus = miibus;
|
|
|
|
miibus->read = tse_phy_read;
|
|
miibus->write = tse_phy_write;
|
|
miibus->priv = priv;
|
|
miibus->parent = dev;
|
|
|
|
if (dev->platform_data != NULL)
|
|
priv->phy_addr = *((int8_t *)(dev->platform_data));
|
|
else
|
|
priv->phy_addr = -1;
|
|
|
|
mdiobus_register(miibus);
|
|
|
|
return eth_register(edev);
|
|
}
|
|
|
|
static struct driver_d altera_tse_driver = {
|
|
.name = "altera_tse",
|
|
.probe = tse_probe,
|
|
};
|
|
device_platform_driver(altera_tse_driver);
|