1244 lines
28 KiB
C
1244 lines
28 KiB
C
/*
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* CPSW Ethernet Switch Driver
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <command.h>
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#include <dma.h>
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#include <net.h>
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#include <malloc.h>
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#include <net.h>
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#include <linux/phy.h>
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#include <errno.h>
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#include <io.h>
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#include <of.h>
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#include <pinctrl.h>
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#include <of_net.h>
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#include <of_address.h>
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#include <xfuncs.h>
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#include <asm/system.h>
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#include <linux/err.h>
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#include <mach/cpsw.h>
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#define CPSW_VERSION_1 0x19010a
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#define CPSW_VERSION_2 0x19010c
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#define BITMASK(bits) ((1 << (bits)) - 1)
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#define PHY_REG_MASK 0x1f
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#define PHY_ID_MASK 0x1f
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#define NUM_DESCS (PKTBUFSRX * 2)
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#define PKT_MIN 60
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#define PKT_MAX (1500 + 14 + 4 + 4)
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/* DMA Registers */
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#define CPDMA_TXCONTROL 0x004
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#define CPDMA_RXCONTROL 0x014
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#define CPDMA_SOFTRESET 0x01c
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#define CPDMA_RXFREE 0x0e0
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#define STATERAM_TXHDP 0x000
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#define STATERAM_RXHDP 0x020
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#define STATERAM_TXCP 0x040
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#define STATERAM_RXCP 0x060
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#define CPDMA_RAM_ADDR 0x4a102000
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/* Descriptor mode bits */
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#define CPDMA_DESC_SOP BIT(31)
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#define CPDMA_DESC_EOP BIT(30)
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#define CPDMA_DESC_OWNER BIT(29)
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#define CPDMA_DESC_EOQ BIT(28)
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#define SLIVER_SIZE 0x40
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struct cpsw_mdio_regs {
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u32 version;
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u32 control;
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#define CONTROL_IDLE (1 << 31)
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#define CONTROL_ENABLE (1 << 30)
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u32 alive;
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u32 link;
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u32 linkintraw;
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u32 linkintmasked;
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u32 __reserved_0[2];
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u32 userintraw;
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u32 userintmasked;
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u32 userintmaskset;
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u32 userintmaskclr;
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u32 __reserved_1[20];
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struct {
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u32 access;
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u32 physel;
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#define USERACCESS_GO (1 << 31)
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#define USERACCESS_WRITE (1 << 30)
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#define USERACCESS_ACK (1 << 29)
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#define USERACCESS_READ (0)
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#define USERACCESS_DATA (0xffff)
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} user[0];
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};
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struct cpsw_regs {
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u32 id_ver;
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u32 control;
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u32 soft_reset;
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u32 stat_port_en;
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u32 ptype;
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};
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struct cpsw_slave_regs {
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u32 max_blks;
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u32 blk_cnt;
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u32 flow_thresh;
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u32 port_vlan;
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u32 tx_pri_map;
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u32 sa_lo;
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u32 sa_hi;
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};
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struct cpsw_host_regs {
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u32 max_blks;
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u32 blk_cnt;
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u32 flow_thresh;
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u32 port_vlan;
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u32 tx_pri_map;
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u32 cpdma_tx_pri_map;
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u32 cpdma_rx_chan_map;
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};
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struct cpsw_sliver_regs {
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u32 id_ver;
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u32 mac_control;
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u32 mac_status;
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u32 soft_reset;
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u32 rx_maxlen;
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u32 __reserved_0;
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u32 rx_pause;
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u32 tx_pause;
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u32 __reserved_1;
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u32 rx_pri_map;
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};
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#define ALE_ENTRY_BITS 68
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#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
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/* ALE Registers */
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#define ALE_CONTROL 0x08
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#define ALE_UNKNOWNVLAN 0x18
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#define ALE_TABLE_CONTROL 0x20
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#define ALE_TABLE 0x34
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#define ALE_PORTCTL 0x40
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#define ALE_TABLE_WRITE BIT(31)
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#define ALE_TYPE_FREE 0
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#define ALE_TYPE_ADDR 1
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#define ALE_TYPE_VLAN 2
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#define ALE_TYPE_VLAN_ADDR 3
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#define ALE_UCAST_PERSISTANT 0
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#define ALE_UCAST_UNTOUCHED 1
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#define ALE_UCAST_OUI 2
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#define ALE_UCAST_TOUCHED 3
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#define ALE_MCAST_FWD 0
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#define ALE_MCAST_BLOCK_LEARN_FWD 1
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#define ALE_MCAST_FWD_LEARN 2
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#define ALE_MCAST_FWD_2 3
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enum cpsw_ale_port_state {
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ALE_PORT_STATE_DISABLE = 0x00,
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ALE_PORT_STATE_BLOCK = 0x01,
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ALE_PORT_STATE_LEARN = 0x02,
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ALE_PORT_STATE_FORWARD = 0x03,
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};
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/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
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#define ALE_SECURE 1
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#define ALE_BLOCKED 2
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struct cpsw_slave {
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struct cpsw_slave_regs *regs;
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struct cpsw_sliver_regs *sliver;
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int slave_num;
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int phy_id;
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phy_interface_t phy_if;
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struct eth_device edev;
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struct cpsw_priv *cpsw;
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struct device_d dev;
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};
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struct cpdma_desc {
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/* hardware fields */
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u32 hw_next;
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u32 hw_buffer;
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u32 hw_len;
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u32 hw_mode;
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/* software fields */
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u32 sw_buffer;
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u32 sw_len;
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};
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struct cpdma_chan {
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struct cpdma_desc *head, *tail;
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void *hdp, *cp, *rxfree;
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};
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struct cpsw_priv {
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struct device_d *dev;
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struct mii_bus miibus;
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u32 version;
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struct cpsw_platform_data data;
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int host_port;
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uint8_t mac_addr[6];
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struct cpsw_regs *regs;
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struct cpsw_mdio_regs *mdio_regs;
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void *dma_regs;
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struct cpsw_host_regs *host_port_regs;
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void *ale_regs;
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void *state_ram;
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unsigned int ale_entries;
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unsigned int num_slaves;
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unsigned int channels;
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unsigned int slave_ofs;
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unsigned int slave_size;
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unsigned int sliver_ofs;
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struct cpdma_desc *descs;
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struct cpdma_desc *desc_free;
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struct cpdma_chan rx_chan, tx_chan;
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struct cpsw_slave *slaves;
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};
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static int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
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{
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int idx;
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idx = start / 32;
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start -= idx * 32;
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idx = 2 - idx; /* flip */
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return (ale_entry[idx] >> start) & BITMASK(bits);
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}
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static void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
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u32 value)
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{
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int idx;
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value &= BITMASK(bits);
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idx = start / 32;
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start -= idx * 32;
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idx = 2 - idx; /* flip */
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ale_entry[idx] &= ~(BITMASK(bits) << start);
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ale_entry[idx] |= (value << start);
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}
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#define DEFINE_ALE_FIELD(name, start, bits) \
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static inline int cpsw_ale_get_##name(u32 *ale_entry) \
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{ \
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return cpsw_ale_get_field(ale_entry, start, bits); \
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} \
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static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
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{ \
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cpsw_ale_set_field(ale_entry, start, bits, value); \
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}
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DEFINE_ALE_FIELD(entry_type, 60, 2)
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DEFINE_ALE_FIELD(mcast_state, 62, 2)
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DEFINE_ALE_FIELD(port_mask, 66, 3)
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DEFINE_ALE_FIELD(ucast_type, 62, 2)
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DEFINE_ALE_FIELD(port_num, 66, 2)
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DEFINE_ALE_FIELD(blocked, 65, 1)
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DEFINE_ALE_FIELD(secure, 64, 1)
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DEFINE_ALE_FIELD(mcast, 40, 1)
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static char ethbdaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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/* The MAC address field in the ALE entry cannot be macroized as above */
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static void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
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{
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int i;
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for (i = 0; i < 6; i++)
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addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
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}
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static void cpsw_ale_set_addr(u32 *ale_entry, u8 *addr)
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{
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int i;
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for (i = 0; i < 6; i++)
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cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
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}
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static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry)
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{
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int i;
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writel(idx, priv->ale_regs + ALE_TABLE_CONTROL);
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for (i = 0; i < ALE_ENTRY_WORDS; i++)
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ale_entry[i] = readl(priv->ale_regs + ALE_TABLE + 4 * i);
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return idx;
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}
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static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry)
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{
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int i;
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for (i = 0; i < ALE_ENTRY_WORDS; i++)
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writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i);
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writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL);
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return idx;
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}
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static int cpsw_ale_match_addr(struct cpsw_priv *priv, u8* addr)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int type, idx;
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for (idx = 0; idx < priv->ale_entries; idx++) {
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u8 entry_addr[6];
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cpsw_ale_read(priv, idx, ale_entry);
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type = cpsw_ale_get_entry_type(ale_entry);
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if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
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continue;
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cpsw_ale_get_addr(ale_entry, entry_addr);
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if (memcmp(entry_addr, addr, 6) == 0)
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return idx;
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}
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return -ENOENT;
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}
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static int cpsw_ale_match_free(struct cpsw_priv *priv)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int type, idx;
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for (idx = 0; idx < priv->ale_entries; idx++) {
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cpsw_ale_read(priv, idx, ale_entry);
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type = cpsw_ale_get_entry_type(ale_entry);
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if (type == ALE_TYPE_FREE)
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return idx;
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}
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return -ENOENT;
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}
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static int cpsw_ale_find_ageable(struct cpsw_priv *priv)
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{
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u32 ale_entry[ALE_ENTRY_WORDS];
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int type, idx;
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for (idx = 0; idx < priv->ale_entries; idx++) {
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cpsw_ale_read(priv, idx, ale_entry);
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type = cpsw_ale_get_entry_type(ale_entry);
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if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
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continue;
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if (cpsw_ale_get_mcast(ale_entry))
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continue;
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type = cpsw_ale_get_ucast_type(ale_entry);
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if (type != ALE_UCAST_PERSISTANT &&
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type != ALE_UCAST_OUI)
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return idx;
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}
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return -ENOENT;
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}
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static int cpsw_ale_add_ucast(struct cpsw_priv *priv, u8 *addr,
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int port, int flags)
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{
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u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
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int idx;
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
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cpsw_ale_set_addr(ale_entry, addr);
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cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
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cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
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cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
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cpsw_ale_set_port_num(ale_entry, port);
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idx = cpsw_ale_match_addr(priv, addr);
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if (idx < 0)
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idx = cpsw_ale_match_free(priv);
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if (idx < 0)
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idx = cpsw_ale_find_ageable(priv);
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if (idx < 0)
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return -ENOMEM;
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cpsw_ale_write(priv, idx, ale_entry);
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return 0;
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}
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static int cpsw_ale_add_mcast(struct cpsw_priv *priv, u8 *addr, int port_mask)
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{
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u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
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int idx, mask;
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idx = cpsw_ale_match_addr(priv, addr);
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if (idx >= 0)
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cpsw_ale_read(priv, idx, ale_entry);
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cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
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cpsw_ale_set_addr(ale_entry, addr);
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cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2);
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mask = cpsw_ale_get_port_mask(ale_entry);
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port_mask |= mask;
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cpsw_ale_set_port_mask(ale_entry, port_mask);
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if (idx < 0)
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idx = cpsw_ale_match_free(priv);
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if (idx < 0)
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idx = cpsw_ale_find_ageable(priv);
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if (idx < 0)
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return -ENOMEM;
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cpsw_ale_write(priv, idx, ale_entry);
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return 0;
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}
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static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val)
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{
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u32 tmp, mask = BIT(bit);
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tmp = readl(priv->ale_regs + ALE_CONTROL);
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tmp &= ~mask;
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tmp |= val ? mask : 0;
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writel(tmp, priv->ale_regs + ALE_CONTROL);
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}
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#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val)
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#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val)
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#define cpsw_ale_bypass(priv, val) cpsw_ale_control(priv, 4, val)
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#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val)
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static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port,
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int val)
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{
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int offset = ALE_PORTCTL + 4 * port;
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u32 tmp, mask = 0x3;
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tmp = readl(priv->ale_regs + offset);
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tmp &= ~mask;
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tmp |= val & 0x3;
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writel(tmp, priv->ale_regs + offset);
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}
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/* wait until hardware is ready for another user access */
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static u32 wait_for_user_access(struct cpsw_priv *priv)
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{
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struct cpsw_mdio_regs *mdio_regs = priv->mdio_regs;
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u32 tmp;
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uint64_t start = get_time_ns();
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do {
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tmp = readl(&mdio_regs->user[0].access);
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if (!(tmp & USERACCESS_GO))
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break;
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if (is_timeout(start, 100 * MSECOND)) {
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dev_err(priv->dev, "timeout waiting for user access\n");
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break;
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}
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} while (1);
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return tmp;
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}
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static int cpsw_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
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{
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struct cpsw_priv *priv = bus->priv;
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struct cpsw_mdio_regs *mdio_regs = priv->mdio_regs;
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u32 tmp;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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wait_for_user_access(priv);
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tmp = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
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(phy_id << 16));
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writel(tmp, &mdio_regs->user[0].access);
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tmp = wait_for_user_access(priv);
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return (tmp & USERACCESS_ACK) ? (tmp & USERACCESS_DATA) : -1;
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}
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static int cpsw_mdio_write(struct mii_bus *bus, int phy_id, int phy_reg, u16 value)
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{
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struct cpsw_priv *priv = bus->priv;
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struct cpsw_mdio_regs *mdio_regs = priv->mdio_regs;
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u32 tmp;
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if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
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return -EINVAL;
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|
|
wait_for_user_access(priv);
|
|
tmp = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
|
|
(phy_id << 16) | (value & USERACCESS_DATA));
|
|
writel(tmp, &mdio_regs->user[0].access);
|
|
wait_for_user_access(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline void soft_reset(struct cpsw_priv *priv, void *reg)
|
|
{
|
|
int ret;
|
|
|
|
writel(1, reg);
|
|
|
|
ret = wait_on_timeout(100 * MSECOND, (readl(reg) & 1) == 0);
|
|
if (ret)
|
|
dev_err(priv->dev, "reset timeout\n");
|
|
}
|
|
|
|
#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
|
|
((mac)[2] << 16) | ((mac)[3] << 24))
|
|
#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
|
|
|
|
static int cpsw_get_hwaddr(struct eth_device *edev, unsigned char *mac)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int cpsw_set_hwaddr(struct eth_device *edev, unsigned char *mac)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
struct cpsw_priv *priv = slave->cpsw;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
memcpy(&priv->mac_addr, mac, sizeof(priv->mac_addr));
|
|
|
|
writel(mac_hi(mac), &slave->regs->sa_hi);
|
|
writel(mac_lo(mac), &slave->regs->sa_lo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cpsw_slave_update_link(struct cpsw_slave *slave,
|
|
struct cpsw_priv *priv, int *link)
|
|
{
|
|
struct phy_device *phydev = slave->edev.phydev;
|
|
u32 mac_control = 0;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
if (!phydev)
|
|
return;
|
|
|
|
if (phydev->link) {
|
|
*link = 1;
|
|
mac_control = BIT(5); /* MIIEN */
|
|
if (phydev->speed == SPEED_10)
|
|
mac_control |= BIT(18); /* In Band mode */
|
|
else if (phydev->speed == SPEED_100)
|
|
mac_control |= BIT(15);
|
|
else if (phydev->speed == SPEED_1000)
|
|
mac_control |= BIT(7);
|
|
if (phydev->duplex == DUPLEX_FULL)
|
|
mac_control |= BIT(0); /* FULLDUPLEXEN */
|
|
}
|
|
|
|
if (mac_control) {
|
|
dev_dbg(&slave->dev, "link up, speed %d, %s duplex\n",
|
|
phydev->speed,
|
|
(phydev->duplex == DUPLEX_FULL) ? "full" : "half");
|
|
} else {
|
|
dev_dbg(&slave->dev, "link down\n");
|
|
}
|
|
|
|
writel(mac_control, &slave->sliver->mac_control);
|
|
}
|
|
|
|
static int cpsw_update_link(struct cpsw_slave *slave, struct cpsw_priv *priv)
|
|
{
|
|
int link = 0;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
cpsw_slave_update_link(slave, priv, &link);
|
|
|
|
return link;
|
|
}
|
|
|
|
static void cpsw_adjust_link(struct eth_device *edev)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
struct cpsw_priv *priv = slave->cpsw;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
cpsw_update_link(slave, priv);
|
|
}
|
|
|
|
static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
|
|
{
|
|
if (priv->host_port == 0)
|
|
return slave_num + 1;
|
|
else
|
|
return slave_num;
|
|
}
|
|
|
|
static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
|
|
{
|
|
u32 slave_port;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
soft_reset(priv, &slave->sliver->soft_reset);
|
|
|
|
/* setup priority mapping */
|
|
writel(0x76543210, &slave->sliver->rx_pri_map);
|
|
writel(0x33221100, &slave->regs->tx_pri_map);
|
|
|
|
/* setup max packet size, and mac address */
|
|
writel(PKT_MAX, &slave->sliver->rx_maxlen);
|
|
|
|
/* enable forwarding */
|
|
slave_port = cpsw_get_slave_port(priv, slave->slave_num);
|
|
cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD);
|
|
|
|
/* add broadcast address */
|
|
cpsw_ale_add_mcast(priv, ethbdaddr, 1 << slave_port);
|
|
}
|
|
|
|
static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv)
|
|
{
|
|
struct cpdma_desc *desc = priv->desc_free;
|
|
|
|
if (desc)
|
|
priv->desc_free = (void *)readl(&desc->hw_next);
|
|
|
|
return desc;
|
|
}
|
|
|
|
static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc)
|
|
{
|
|
dev_dbg(priv->dev, "%s: free desc=0x%p\n", __func__, desc);
|
|
|
|
if (desc) {
|
|
writel((u32)priv->desc_free, &desc->hw_next);
|
|
priv->desc_free = desc;
|
|
}
|
|
}
|
|
|
|
static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan,
|
|
void *buffer, int len)
|
|
{
|
|
struct cpdma_desc *desc, *prev;
|
|
u32 mode;
|
|
|
|
desc = cpdma_desc_alloc(priv);
|
|
if (!desc)
|
|
return -ENOMEM;
|
|
|
|
if (len < PKT_MIN)
|
|
len = PKT_MIN;
|
|
|
|
mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP;
|
|
|
|
writel(0, &desc->hw_next);
|
|
writel((u32)buffer, &desc->hw_buffer);
|
|
writel(len, &desc->hw_len);
|
|
writel(mode | len, &desc->hw_mode);
|
|
writel((u32)buffer, &desc->sw_buffer);
|
|
writel((u32)len, &desc->sw_len);
|
|
|
|
if (!chan->head) {
|
|
/* simple case - first packet enqueued */
|
|
chan->head = desc;
|
|
chan->tail = desc;
|
|
writel((u32)desc, chan->hdp);
|
|
goto done;
|
|
}
|
|
|
|
/* not the first packet - enqueue at the tail */
|
|
prev = chan->tail;
|
|
writel((u32)desc, &prev->hw_next);
|
|
chan->tail = desc;
|
|
|
|
/* next check if EOQ has been triggered already */
|
|
if (readl(&prev->hw_mode) & CPDMA_DESC_EOQ)
|
|
writel((u32)desc, chan->hdp);
|
|
|
|
done:
|
|
if (chan->rxfree)
|
|
writel(1, chan->rxfree);
|
|
return 0;
|
|
}
|
|
|
|
static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan,
|
|
void **buffer, int *len)
|
|
{
|
|
struct cpdma_desc *desc = chan->head;
|
|
u32 status;
|
|
|
|
if (!desc)
|
|
return -ENOENT;
|
|
|
|
status = readl(&desc->hw_mode);
|
|
|
|
if (len)
|
|
*len = status & 0x7ff;
|
|
|
|
if (buffer)
|
|
*buffer = (void *)readl(&desc->sw_buffer);
|
|
|
|
if (status & CPDMA_DESC_OWNER) {
|
|
if (readl(chan->hdp) == 0) {
|
|
if (readl(&desc->hw_mode) & CPDMA_DESC_OWNER)
|
|
writel((u32)desc, chan->hdp);
|
|
}
|
|
return -EBUSY;
|
|
}
|
|
|
|
chan->head = (void *)readl(&desc->hw_next);
|
|
|
|
writel((u32)desc, chan->cp);
|
|
|
|
cpdma_desc_free(priv, desc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cpsw_init(struct eth_device *edev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int cpsw_open(struct eth_device *edev)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
struct cpsw_priv *priv = slave->cpsw;
|
|
int i, ret;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
ret = phy_device_connect(edev, &priv->miibus, slave->phy_id,
|
|
cpsw_adjust_link, 0, slave->phy_if);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* soft reset the controller and initialize priv */
|
|
soft_reset(priv, &priv->regs->soft_reset);
|
|
|
|
/* initialize and reset the address lookup engine */
|
|
cpsw_ale_enable(priv, 1);
|
|
cpsw_ale_clear(priv, 1);
|
|
cpsw_ale_bypass(priv, 0);
|
|
cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */
|
|
|
|
/* setup host port priority mapping */
|
|
writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map);
|
|
writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
|
|
|
|
/* disable priority elevation and enable statistics on all ports */
|
|
writel(0, &priv->regs->ptype);
|
|
|
|
/* enable statistics collection only on the host port */
|
|
writel(BIT(priv->host_port), &priv->regs->stat_port_en);
|
|
|
|
cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD);
|
|
|
|
cpsw_ale_add_ucast(priv, priv->mac_addr, priv->host_port,
|
|
ALE_SECURE);
|
|
cpsw_ale_add_mcast(priv, ethbdaddr, 1 << priv->host_port);
|
|
|
|
cpsw_slave_init(slave, priv);
|
|
cpsw_update_link(slave, priv);
|
|
|
|
/* init descriptor pool */
|
|
for (i = 0; i < NUM_DESCS; i++) {
|
|
u32 val = (i == (NUM_DESCS - 1)) ? 0 : (u32)&priv->descs[i + 1];
|
|
|
|
writel(val, &priv->descs[i].hw_next);
|
|
}
|
|
|
|
priv->desc_free = &priv->descs[0];
|
|
|
|
/* initialize channels */
|
|
memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan));
|
|
priv->rx_chan.hdp = priv->state_ram + STATERAM_RXHDP;
|
|
priv->rx_chan.cp = priv->state_ram + STATERAM_RXCP;
|
|
priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE;
|
|
|
|
memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan));
|
|
priv->tx_chan.hdp = priv->state_ram + STATERAM_TXHDP;
|
|
priv->tx_chan.cp = priv->state_ram + STATERAM_TXCP;
|
|
|
|
/* clear dma state */
|
|
soft_reset(priv, priv->dma_regs + CPDMA_SOFTRESET);
|
|
|
|
for (i = 0; i < priv->channels; i++) {
|
|
writel(0, priv->state_ram + STATERAM_RXHDP + 4 * i);
|
|
writel(0, priv->dma_regs + CPDMA_RXFREE + 4 * i);
|
|
writel(0, priv->state_ram + STATERAM_RXCP + 4 * i);
|
|
writel(0, priv->state_ram + STATERAM_TXHDP + 4 * i);
|
|
writel(0, priv->state_ram + STATERAM_TXCP + 4 * i);
|
|
}
|
|
|
|
writel(1, priv->dma_regs + CPDMA_TXCONTROL);
|
|
writel(1, priv->dma_regs + CPDMA_RXCONTROL);
|
|
|
|
/* submit rx descs */
|
|
for (i = 0; i < PKTBUFSRX - 2; i++) {
|
|
ret = cpdma_submit(priv, &priv->rx_chan, NetRxPackets[i],
|
|
PKTSIZE);
|
|
if (ret < 0) {
|
|
dev_err(&slave->dev, "error %d submitting rx desc\n", ret);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cpsw_halt(struct eth_device *edev)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
struct cpsw_priv *priv = slave->cpsw;
|
|
|
|
dev_dbg(priv->dev, "* %s slave %d\n", __func__, slave->slave_num);
|
|
|
|
writel(0, priv->dma_regs + CPDMA_TXCONTROL);
|
|
writel(0, priv->dma_regs + CPDMA_RXCONTROL);
|
|
|
|
/* soft reset the controller */
|
|
soft_reset(priv, &priv->regs->soft_reset);
|
|
|
|
/* clear dma state */
|
|
soft_reset(priv, priv->dma_regs + CPDMA_SOFTRESET);
|
|
}
|
|
|
|
static int cpsw_send(struct eth_device *edev, void *packet, int length)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
struct cpsw_priv *priv = slave->cpsw;
|
|
void *buffer;
|
|
int ret, len;
|
|
|
|
dev_dbg(&slave->dev, "* %s slave %d\n", __func__, slave->slave_num);
|
|
|
|
/* first reap completed packets */
|
|
while (cpdma_process(priv, &priv->tx_chan, &buffer, &len) >= 0);
|
|
|
|
dev_dbg(&slave->dev, "%s: %i bytes @ 0x%p\n", __func__, length, packet);
|
|
|
|
dma_sync_single_for_device((unsigned long)packet, length, DMA_TO_DEVICE);
|
|
ret = cpdma_submit(priv, &priv->tx_chan, packet, length);
|
|
dma_sync_single_for_cpu((unsigned long)packet, length, DMA_TO_DEVICE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int cpsw_recv(struct eth_device *edev)
|
|
{
|
|
struct cpsw_slave *slave = edev->priv;
|
|
struct cpsw_priv *priv = slave->cpsw;
|
|
void *buffer;
|
|
int len;
|
|
|
|
while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
|
|
dma_sync_single_for_cpu((unsigned long)buffer, len,
|
|
DMA_FROM_DEVICE);
|
|
net_receive(edev, buffer, len);
|
|
dma_sync_single_for_device((unsigned long)buffer, len,
|
|
DMA_FROM_DEVICE);
|
|
cpdma_submit(priv, &priv->rx_chan, buffer, PKTSIZE);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cpsw_slave_init_data(struct cpsw_slave *slave, int slave_num,
|
|
struct cpsw_priv *priv)
|
|
{
|
|
struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
|
|
|
|
slave->phy_id = data->phy_id;
|
|
slave->phy_if = data->phy_if;
|
|
}
|
|
|
|
static int cpsw_slave_setup(struct cpsw_slave *slave, int slave_num,
|
|
struct cpsw_priv *priv)
|
|
{
|
|
void *regs = priv->regs;
|
|
struct eth_device *edev = &slave->edev;
|
|
struct device_d *dev = &slave->dev;
|
|
int ret;
|
|
struct phy_device *phy;
|
|
|
|
phy = mdiobus_scan(&priv->miibus, priv->slaves[slave_num].phy_id);
|
|
if (IS_ERR(phy))
|
|
return PTR_ERR(phy);
|
|
|
|
phy->dev.device_node = priv->slaves[slave_num].dev.device_node;
|
|
ret = phy_register_device(phy);
|
|
if (ret)
|
|
return ret;
|
|
|
|
sprintf(dev->name, "cpsw-slave");
|
|
dev->id = slave->slave_num;
|
|
dev->parent = priv->dev;
|
|
ret = register_device(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_dbg(&slave->dev, "* %s\n", __func__);
|
|
|
|
slave->slave_num = slave_num;
|
|
slave->regs = regs + priv->slave_ofs + priv->slave_size * slave_num;
|
|
slave->sliver = regs + priv->sliver_ofs + SLIVER_SIZE * slave_num;
|
|
slave->cpsw = priv;
|
|
|
|
edev->priv = slave;
|
|
edev->init = cpsw_init;
|
|
edev->open = cpsw_open;
|
|
edev->halt = cpsw_halt;
|
|
edev->send = cpsw_send;
|
|
edev->recv = cpsw_recv;
|
|
edev->get_ethaddr = cpsw_get_hwaddr;
|
|
edev->set_ethaddr = cpsw_set_hwaddr;
|
|
edev->parent = dev;
|
|
|
|
return eth_register(edev);
|
|
}
|
|
|
|
struct cpsw_data {
|
|
unsigned int host_port_reg_ofs;
|
|
unsigned int cpdma_reg_ofs;
|
|
unsigned int ale_reg_ofs;
|
|
unsigned int state_ram_ofs;
|
|
unsigned int slave_ofs;
|
|
unsigned int slave_size;
|
|
unsigned int sliver_ofs;
|
|
unsigned int mdio_reg_ofs;
|
|
unsigned int cppi_ram_ofs;
|
|
};
|
|
|
|
static struct cpsw_data cpsw1_data = {
|
|
.host_port_reg_ofs = 0x028,
|
|
.cpdma_reg_ofs = 0x100,
|
|
.state_ram_ofs = 0x200,
|
|
.ale_reg_ofs = 0x600,
|
|
.slave_ofs = 0x050,
|
|
.slave_size = 0x040,
|
|
.sliver_ofs = 0x700,
|
|
/* FIXME: mdio_reg_ofs and cppi_ram_ofs missing */
|
|
};
|
|
|
|
static struct cpsw_data cpsw2_data = {
|
|
.host_port_reg_ofs = 0x108,
|
|
.cpdma_reg_ofs = 0x800,
|
|
.state_ram_ofs = 0xa00,
|
|
.ale_reg_ofs = 0xd00,
|
|
.slave_ofs = 0x200,
|
|
.slave_size = 0x100,
|
|
.sliver_ofs = 0xd80,
|
|
.mdio_reg_ofs = 0x1000,
|
|
.cppi_ram_ofs = 0x2000,
|
|
};
|
|
|
|
static void __iomem *phy_sel_addr;
|
|
static bool rmii_clock_external;
|
|
|
|
static int cpsw_phy_sel_init(struct cpsw_priv *priv, struct device_node *np)
|
|
{
|
|
const void *reg;
|
|
unsigned long addr;
|
|
|
|
reg = of_get_property(np, "reg", NULL);
|
|
if (!reg)
|
|
return -EINVAL;
|
|
|
|
addr = of_translate_address(np, reg);
|
|
|
|
phy_sel_addr = (void *)addr;
|
|
|
|
if (of_property_read_bool(np, "rmii-clock-ext"))
|
|
rmii_clock_external = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* AM33xx SoC specific definitions for the CONTROL port */
|
|
#define AM33XX_GMII_SEL_MODE_MII 0
|
|
#define AM33XX_GMII_SEL_MODE_RMII 1
|
|
#define AM33XX_GMII_SEL_MODE_RGMII 2
|
|
|
|
#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
|
|
#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
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static void cpsw_gmii_sel_am335x(struct cpsw_slave *slave)
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{
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u32 reg;
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u32 mask;
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u32 mode = 0;
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reg = readl(phy_sel_addr);
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switch (slave->phy_if) {
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case PHY_INTERFACE_MODE_RMII:
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mode = AM33XX_GMII_SEL_MODE_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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mode = AM33XX_GMII_SEL_MODE_RGMII;
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break;
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case PHY_INTERFACE_MODE_MII:
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default:
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mode = AM33XX_GMII_SEL_MODE_MII;
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break;
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};
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mask = 0x3 << (slave->slave_num * 2) | BIT(slave->slave_num + 6);
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mode <<= slave->slave_num * 2;
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if (rmii_clock_external) {
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if (slave->slave_num == 0)
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mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN;
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else
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mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN;
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}
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reg &= ~mask;
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reg |= mode;
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writel(reg, phy_sel_addr);
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}
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static int cpsw_probe_dt(struct cpsw_priv *priv)
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{
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struct device_d *dev = priv->dev;
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struct device_node *np = dev->device_node, *child;
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int ret, i = 0;
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ret = of_property_read_u32(np, "slaves", &priv->num_slaves);
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if (ret)
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return ret;
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priv->slaves = xzalloc(sizeof(struct cpsw_slave) * priv->num_slaves);
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for_each_child_of_node(np, child) {
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if (of_device_is_compatible(child, "ti,am3352-cpsw-phy-sel")) {
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ret = cpsw_phy_sel_init(priv, child);
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if (ret)
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return ret;
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}
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if (of_device_is_compatible(child, "ti,davinci_mdio")) {
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ret = of_pinctrl_select_state_default(child);
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if (ret)
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return ret;
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}
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if (i < priv->num_slaves && !strncmp(child->name, "slave", 5)) {
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struct cpsw_slave *slave = &priv->slaves[i];
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uint32_t phy_id[2];
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ret = of_property_read_u32_array(child, "phy_id", phy_id, 2);
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if (ret)
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return ret;
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slave->dev.device_node = child;
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slave->phy_id = phy_id[1];
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slave->phy_if = of_get_phy_mode(child);
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slave->slave_num = i;
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i++;
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}
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}
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for (i = 0; i < priv->num_slaves; i++) {
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struct cpsw_slave *slave = &priv->slaves[i];
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cpsw_gmii_sel_am335x(slave);
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}
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return 0;
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}
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int cpsw_probe(struct device_d *dev)
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{
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struct cpsw_platform_data *data = (struct cpsw_platform_data *)dev->platform_data;
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struct cpsw_priv *priv;
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void __iomem *regs;
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uint64_t start;
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uint32_t phy_mask;
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struct cpsw_data *cpsw_data;
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int i, ret;
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dev_dbg(dev, "* %s\n", __func__);
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regs = dev_request_mem_region(dev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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priv = xzalloc(sizeof(*priv));
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priv->dev = dev;
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if (dev->device_node) {
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ret = cpsw_probe_dt(priv);
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if (ret)
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goto out;
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} else {
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priv->data = *data;
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priv->num_slaves = data->num_slaves;
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priv->slaves = xzalloc(sizeof(struct cpsw_slave) * priv->num_slaves);
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cpsw_slave_init_data(&priv->slaves[0], 0, priv);
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}
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priv->channels = 8;
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priv->ale_entries = 1024;
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priv->host_port = 0;
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priv->regs = regs;
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priv->version = readl(&priv->regs->id_ver);
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switch (priv->version) {
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case CPSW_VERSION_1:
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cpsw_data = &cpsw1_data;
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break;
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case CPSW_VERSION_2:
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cpsw_data = &cpsw2_data;
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break;
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default:
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ret = -EINVAL;
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goto out;
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}
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priv->descs = regs + cpsw_data->cppi_ram_ofs;
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priv->host_port_regs = regs + cpsw_data->host_port_reg_ofs;
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priv->dma_regs = regs + cpsw_data->cpdma_reg_ofs;
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priv->ale_regs = regs + cpsw_data->ale_reg_ofs;
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priv->state_ram = regs + cpsw_data->state_ram_ofs;
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priv->mdio_regs = regs + cpsw_data->mdio_reg_ofs;
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priv->slave_ofs = cpsw_data->slave_ofs;
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priv->slave_size = cpsw_data->slave_size;
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priv->sliver_ofs = cpsw_data->sliver_ofs;
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priv->miibus.read = cpsw_mdio_read;
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priv->miibus.write = cpsw_mdio_write;
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priv->miibus.priv = priv;
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priv->miibus.parent = dev;
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/*
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* set enable and clock divider
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*
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* FIXME: Use a clock to calculate the divider
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*/
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writel(0xff | CONTROL_ENABLE, &priv->mdio_regs->control);
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/*
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* wait for scan logic to settle:
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* the scan time consists of (a) a large fixed component, and (b) a
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* small component that varies with the mii bus frequency. These
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* were estimated using measurements at 1.1 and 2.2 MHz on tnetv107x
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* silicon. Since the effect of (b) was found to be largely
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* negligible, we keep things simple here.
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*/
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udelay(1000);
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start = get_time_ns();
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while (1) {
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phy_mask = readl(&priv->mdio_regs->alive);
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if (phy_mask) {
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dev_info(dev, "detected phy mask 0x%x\n", phy_mask);
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phy_mask = ~phy_mask;
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break;
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}
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if (is_timeout(start, 256 * MSECOND)) {
|
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dev_err(dev, "no live phy, scanning all\n");
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phy_mask = 0;
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break;
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}
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}
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priv->miibus.phy_mask = phy_mask;
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mdiobus_register(&priv->miibus);
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for (i = 0; i < priv->num_slaves; i++) {
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ret = cpsw_slave_setup(&priv->slaves[i], i, priv);
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if (ret) {
|
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dev_err(dev, "Failed to setup slave %d: %s\n", i, strerror(-ret));
|
|
continue;
|
|
}
|
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}
|
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|
|
return 0;
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out:
|
|
free(priv->slaves);
|
|
free(priv);
|
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|
|
return ret;
|
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}
|
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|
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static __maybe_unused struct of_device_id cpsw_dt_ids[] = {
|
|
{
|
|
.compatible = "ti,cpsw",
|
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}, {
|
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/* sentinel */
|
|
}
|
|
};
|
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|
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static struct driver_d cpsw_driver = {
|
|
.name = "cpsw",
|
|
.probe = cpsw_probe,
|
|
.of_compatible = DRV_OF_COMPAT(cpsw_dt_ids),
|
|
};
|
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device_platform_driver(cpsw_driver);
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