226 lines
7.7 KiB
C
226 lines
7.7 KiB
C
/*
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* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
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*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This file is based on mpc4200fec.h
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* (C) Copyright Motorola, Inc., 2000
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#ifndef __IMX27_FEC_H
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#define __IMX27_FEC_H
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#define FEC_IEVENT 0x004
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#define FEC_IMASK 0x008
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#define FEC_R_DES_ACTIVE 0x010
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#define FEC_X_DES_ACTIVE 0x014
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#define FEC_ECNTRL 0x024
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#define FEC_MII_DATA 0x040
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#define FEC_MII_SPEED 0x044
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#define FEC_R_CNTRL 0x084
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#define FEC_X_CNTRL 0x0c4
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#define FEC_PADDR1 0x0e4
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#define FEC_OP_PAUSE 0x0ec
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#define FEC_PADDR2 0x0e8
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#define FEC_IADDR1 0x118
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#define FEC_IADDR2 0x11c
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#define FEC_GADDR1 0x120
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#define FEC_GADDR2 0x124
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#define FEC_X_WMRK 0x144
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#define FEC_ERDSR 0x180
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#define FEC_ETDSR 0x184
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#define FEC_EMRBR 0x188
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#define FEC_MIIGSK_CFGR 0x300
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#define FEC_MIIGSK_ENR 0x308
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/*
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* Some i.MXs allows RMII mode to be configured via a gasket
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*/
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#define FEC_MIIGSK_CFGR_FRCONT (1 << 6)
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#define FEC_MIIGSK_CFGR_LBMODE (1 << 4)
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#define FEC_MIIGSK_CFGR_EMODE (1 << 3)
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#define FEC_MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
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#define FEC_MIIGSK_CFGR_IF_MODE_MII (0 << 0)
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#define FEC_MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
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#define FEC_MIIGSK_ENR_READY (1 << 2)
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#define FEC_MIIGSK_ENR_EN (1 << 1)
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#define FEC_R_CNTRL_GRS (1 << 31)
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#define FEC_R_CNTRL_NO_LGTH_CHECK (1 << 30)
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#ifdef CONFIG_ARCH_IMX28
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# define FEC_R_CNTRL_MAX_FL(x) (((x) & 0x3fff) << 16)
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#else
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# define FEC_R_CNTRL_MAX_FL(x) (((x) & 0x7ff) << 16)
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#endif
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#define FEC_R_CNTRL_RMII_10T (1 << 9) /* i.MX28 specific */
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#define FEC_R_CNTRL_RMII_MODE (1 << 8) /* i.MX28 specific */
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#define FEC_R_CNTRL_FCE (1 << 5)
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#define FEC_R_CNTRL_MII_MODE (1 << 2)
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#define FEC_IEVENT_HBERR 0x80000000 /* Note: Not on i.MX28 */
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#define FEC_IEVENT_BABR 0x40000000
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#define FEC_IEVENT_BABT 0x20000000
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#define FEC_IEVENT_GRA 0x10000000
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#define FEC_IEVENT_TFINT 0x08000000
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#define FEC_IEVENT_MII 0x00800000
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#define FEC_IEVENT_LATE_COL 0x00200000
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#define FEC_IEVENT_COL_RETRY_LIM 0x00100000
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#define FEC_IEVENT_XFIFO_UN 0x00080000
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#define FEC_IMASK_HBERR 0x80000000 /* Note: Not on i.MX28 */
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#define FEC_IMASK_BABR 0x40000000
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#define FEC_IMASK_BABT 0x20000000
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#define FEC_IMASK_GRA 0x10000000
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#define FEC_IMASK_MII 0x00800000
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#define FEC_IMASK_LATE_COL 0x00200000
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#define FEC_IMASK_COL_RETRY_LIM 0x00100000
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#define FEC_IMASK_XFIFO_UN 0x00080000
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#define FEC_ECNTRL_RESET 0x00000001 /**< reset the FEC */
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#define FEC_ECNTRL_ETHER_EN 0x00000002 /**< enable the FEC */
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#define FEC_ECNTRL_SPEED 0x00000020 /**< i.MX6: enable 1000Mbps mode */
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/**
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* @brief Descriptor buffer alignment
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*
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* i.MX27 requires a 16 byte alignment (but for the first element only)
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*/
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#define DB_ALIGNMENT 16
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/**
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* @brief Data buffer alignment
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*
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* i.MX27 requires a 16 byte alignment
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*
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* Note: Valid for member data_pointer in struct buffer_descriptor
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*/
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#define DB_DATA_ALIGNMENT 16
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/**
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* @brief Receive & Transmit Buffer Descriptor definitions
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*
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* Note: The first BD must be aligned (see DB_ALIGNMENT)
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*
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* BTW: Don't trust the i.MX27 and i.MX28 data sheet
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*/
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struct buffer_descriptor {
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uint16_t data_length; /**< payload's length in bytes */
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uint16_t status; /**< BD's staus (see datasheet) */
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uint32_t data_pointer; /**< payload's buffer address */
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};
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enum fec_type {
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FEC_TYPE_IMX27,
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FEC_TYPE_IMX28,
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FEC_TYPE_IMX6,
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};
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/**
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* @brief i.MX27-FEC private structure
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*/
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struct fec_priv {
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struct eth_device edev;
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void __iomem *regs;
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struct buffer_descriptor __iomem *rbd_base; /* RBD ring */
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int rbd_index; /* next receive BD to read */
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struct buffer_descriptor __iomem *tbd_base; /* TBD ring */
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int tbd_index; /* next transmit BD to write */
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int phy_addr;
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phy_interface_t interface;
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u32 phy_flags;
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struct mii_bus miibus;
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void (*phy_init)(struct phy_device *dev);
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struct clk *clk;
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enum fec_type type;
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};
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static inline int fec_is_imx27(struct fec_priv *priv)
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{
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return priv->type == FEC_TYPE_IMX27;
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}
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static inline int fec_is_imx28(struct fec_priv *priv)
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{
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return priv->type == FEC_TYPE_IMX28;
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}
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static inline int fec_is_imx6(struct fec_priv *priv)
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{
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return priv->type == FEC_TYPE_IMX6;
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}
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/**
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* @brief Numbers of buffer descriptors for receiving
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*
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* The number defines the stocked memory buffers for the receiving task.
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* Larger values makes no sense in this limited environment.
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*/
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#define FEC_RBD_NUM 64
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/**
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* @brief Define the ethernet packet size limit in memory
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*
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* Note: Do not shrink this number. This will force the FEC to spread larger
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* frames in more than one BD. This is nothing to worry about, but the current
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* driver can't handle it.
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*/
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#define FEC_MAX_PKT_SIZE 1536
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/* Receive BD status bits */
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#define FEC_RBD_EMPTY 0x8000 /**< Receive BD status: Buffer is empty */
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#define FEC_RBD_WRAP 0x2000 /**< Receive BD status: Last BD in ring */
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#define FEC_RBD_INT 0x1000 /**< Receive BD status: Interrupt */
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#define FEC_RBD_LAST 0x0800 /**< Receive BD status: Buffer is last in frame (useless here!) */
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#define FEC_RBD_MISS 0x0100 /**< Receive BD status: Miss bit for prom mode */
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#define FEC_RBD_BC 0x0080 /**< Receive BD status: The received frame is broadcast frame */
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#define FEC_RBD_MC 0x0040 /**< Receive BD status: The received frame is multicast frame */
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#define FEC_RBD_LG 0x0020 /**< Receive BD status: Frame length violation */
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#define FEC_RBD_NO 0x0010 /**< Receive BD status: Nonoctet align frame */
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#define FEC_RBD_SH 0x0008 /**< Receive BD status: Short frame */
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#define FEC_RBD_CR 0x0004 /**< Receive BD status: CRC error */
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#define FEC_RBD_OV 0x0002 /**< Receive BD status: Receive FIFO overrun */
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#define FEC_RBD_TR 0x0001 /**< Receive BD status: Frame is truncated */
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#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
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FEC_RBD_OV | FEC_RBD_TR)
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/* Transmit BD status bits */
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#define FEC_TBD_READY 0x8000 /**< Tansmit BD status: Buffer is ready */
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#define FEC_TBD_WRAP 0x2000 /**< Tansmit BD status: Mark as last BD in ring */
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#define FEC_TBD_INT 0x1000 /**< Tansmit BD status: Interrupt */
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#define FEC_TBD_LAST 0x0800 /**< Tansmit BD status: Buffer is last in frame */
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#define FEC_TBD_TC 0x0400 /**< Tansmit BD status: Transmit the CRC */
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#define FEC_TBD_ABC 0x0200 /**< Tansmit BD status: Append bad CRC */
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/* MII-related definitios */
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#define FEC_MII_DATA_ST 0x40000000 /**< Start of frame delimiter */
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#define FEC_MII_DATA_OP_RD 0x20000000 /**< Perform a read operation */
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#define FEC_MII_DATA_OP_WR 0x10000000 /**< Perform a write operation */
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#define FEC_MII_DATA_PA_MSK 0x0f800000 /**< PHY Address field mask */
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#define FEC_MII_DATA_RA_MSK 0x007c0000 /**< PHY Register field mask */
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#define FEC_MII_DATA_TA 0x00020000 /**< Turnaround */
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#define FEC_MII_DATA_DATAMSK 0x0000ffff /**< PHY data field */
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#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
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#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
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#endif /* __IMX27_FEC_H */
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/**
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* @file
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* @brief Definitions for the FEC driver (i.MX27)
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*/
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