773 lines
24 KiB
C
773 lines
24 KiB
C
/*
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* (C) Copyright 2014 - Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
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*
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* based on mvneta driver from linux
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* (C) Copyright 2012 Marvell
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* Rami Rosen <rosenr@marvell.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* based on orion-gbe driver from barebox
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* (C) Copyright 2014
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* Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <dma.h>
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#include <init.h>
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#include <io.h>
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#include <net.h>
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#include <of_net.h>
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#include <linux/sizes.h>
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#include <asm/mmu.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mbus.h>
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/* Registers */
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/* Rx queue */
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#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
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#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
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#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
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#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
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#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
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#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
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#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
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#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
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#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
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#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
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#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
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#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
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#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
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#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
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#define MVNETA_PORT_RX_RESET 0x1cc0
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#define MVNETA_MBUS_RETRY 0x2010
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#define MVNETA_UNIT_INTR_CAUSE 0x2080
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#define MVNETA_UNIT_CONTROL 0x20B0
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#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
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#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
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#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
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#define MVNETA_BASE_ADDR_ENABLE 0x2290
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#define MVNETA_PORT_CONFIG 0x2400
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#define MVNETA_DEF_RXQ(q) ((q) << 1)
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#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
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#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
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#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
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#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
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#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
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#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
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#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
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MVNETA_DEF_RXQ_ARP(q) | \
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MVNETA_DEF_RXQ_TCP(q) | \
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MVNETA_DEF_RXQ_UDP(q) | \
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MVNETA_DEF_RXQ_BPDU(q) | \
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MVNETA_TX_UNSET_ERR_SUM | \
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MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
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#define MVNETA_PORT_CONFIG_EXTEND 0x2404
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#define MVNETA_MAC_ADDR_LOW 0x2414
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#define MVNETA_MAC_ADDR_HIGH 0x2418
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#define MVNETA_SDMA_CONFIG 0x241c
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#define MVNETA_SDMA_BRST_SIZE_16 4
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#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
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#define MVNETA_RX_NO_DATA_SWAP BIT(4)
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#define MVNETA_TX_NO_DATA_SWAP BIT(5)
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#define MVNETA_DESC_SWAP BIT(6)
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#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
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#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
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#define MVNETA_SERDES_CFG 0x24a0
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#define MVNETA_SGMII_SERDES 0x0cc7
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#define MVNETA_QSGMII_SERDES 0x0667
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#define MVNETA_TYPE_PRIO 0x24bc
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#define MVNETA_TXQ_CMD_1 0x24e4
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#define MVNETA_TXQ_CMD 0x2448
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#define MVNETA_TXQ_DISABLE_SHIFT 8
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#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
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#define MVNETA_ACC_MODE 0x2500
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#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
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#define MVNETA_INTR_NEW_CAUSE 0x25a0
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#define MVNETA_INTR_NEW_MASK 0x25a4
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#define MVNETA_INTR_OLD_CAUSE 0x25a8
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#define MVNETA_INTR_OLD_MASK 0x25ac
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#define MVNETA_INTR_MISC_CAUSE 0x25b0
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#define MVNETA_INTR_MISC_MASK 0x25b4
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#define MVNETA_INTR_ENABLE 0x25b8
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#define MVNETA_RXQ_CMD 0x2680
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#define MVNETA_RXQ_DISABLE_SHIFT 8
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#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
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#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
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#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
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#define MVNETA_GMAC_CTRL_0 0x2c00
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#define MVNETA_GMAC_CTRL_2 0x2c08
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#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
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#define MVNETA_GMAC2_PORT_RGMII BIT(4)
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#define MVNETA_GMAC2_PORT_RESET BIT(6)
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#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
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#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
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#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
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#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
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#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
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#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
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#define MVNETA_GMAC_CONFIG_FLOWCTRL BIT(8)
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#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
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#define MVNETA_GMAC_AN_FLOWCTRL_EN BIT(11)
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#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
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#define MVNETA_MIB_COUNTERS_BASE 0x3080
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#define MVNETA_MIB_LATE_COLLISION 0x7c
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#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
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#define MVNETA_DA_FILT_OTH_MCAST 0x3500
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#define MVNETA_DA_FILT_UCAST_BASE 0x3600
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#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
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#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
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#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
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#define MVNETA_TXQ_DEC_SENT_SHIFT 16
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#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
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#define MVNETA_PORT_TX_RESET 0x3cf0
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#define MVNETA_TX_MTU 0x3e0c
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#define MVNETA_TX_TOKEN_SIZE 0x3e14
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#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
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/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
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* layout of the transmit and reception DMA descriptors, and their
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* layout is therefore defined by the hardware design
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*/
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#define MVNETA_TX_L3_OFF_SHIFT 0
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#define MVNETA_TX_IP_HLEN_SHIFT 8
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#define MVNETA_TX_L4_UDP BIT(16)
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#define MVNETA_TX_L3_IP6 BIT(17)
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#define MVNETA_TXD_IP_CSUM BIT(18)
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#define MVNETA_TXD_Z_PAD BIT(19)
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#define MVNETA_TXD_L_DESC BIT(20)
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#define MVNETA_TXD_F_DESC BIT(21)
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#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
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MVNETA_TXD_L_DESC | \
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MVNETA_TXD_F_DESC)
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#define MVNETA_TX_L4_CSUM_FULL BIT(30)
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#define MVNETA_TX_L4_CSUM_NOT BIT(31)
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#define MVNETA_TXD_ERROR BIT(0)
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#define TXD_ERROR_MASK 0x6
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#define TXD_ERROR_SHIFT 1
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#define MVNETA_RXD_ERR_CRC 0x0
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#define MVNETA_RXD_ERR_SUMMARY BIT(16)
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#define MVNETA_RXD_ERR_OVERRUN BIT(17)
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#define MVNETA_RXD_ERR_LEN BIT(18)
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#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
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#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
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#define MVNETA_RXD_L3_IP4 BIT(25)
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#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
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#define MVNETA_RXD_L4_CSUM_OK BIT(30)
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#define MVNETA_MH_SIZE 2
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#define TXQ_NUM 8
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#define RX_RING_SIZE 4
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#define TRANSFER_TIMEOUT (10 * MSECOND)
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struct rxdesc {
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u32 cmd_sts; /* Info about received packet */
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u16 reserved1; /* pnc_info - (for future use, PnC) */
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u16 data_size; /* Size of received packet in bytes */
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u32 buf_phys_addr; /* Physical address of the buffer */
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u32 reserved2; /* pnc_flow_id (for future use, PnC) */
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u32 buf_cookie; /* cookie for access to RX buffer in rx path */
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u16 reserved3; /* prefetch_cmd, for future use */
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u16 reserved4; /* csum_l4 - (for future use, PnC) */
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u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
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u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
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};
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struct txdesc {
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u32 cmd_sts; /* Options used by HW for packet transmitting.*/
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u16 reserverd1; /* csum_l4 (for future use) */
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u16 byte_cnt; /* Data size of transmitted packet in bytes */
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u32 buf_ptr; /* Physical addr of transmitted buffer */
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u8 error; /* */
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u8 reserved2; /* Reserved - (for future use) */
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u16 reserved3; /* Reserved - (for future use) */
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u32 reserved4[4]; /* Reserved - (for future use) */
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};
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struct mvneta_port {
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void __iomem *reg;
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struct device_d dev;
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struct eth_device edev;
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struct clk *clk;
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struct txdesc *txdesc;
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struct rxdesc *rxdesc;
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int curr_rxdesc;
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u8 *rxbuf;
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phy_interface_t intf;
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};
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static void mvneta_conf_mbus_windows(struct mvneta_port *priv)
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{
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const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
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u32 win_enable, win_protect;
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int i;
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for (i = 0; i < 6; i++) {
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writel(0, priv->reg + MVNETA_WIN_BASE(i));
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writel(0, priv->reg + MVNETA_WIN_SIZE(i));
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if (i < 4)
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writel(0, priv->reg + MVNETA_WIN_REMAP(i));
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}
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win_enable = 0x3f;
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win_protect = 0;
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel((cs->base & 0xffff0000) |
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(cs->mbus_attr << 8) |
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dram->mbus_dram_target_id,
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priv->reg + MVNETA_WIN_BASE(i));
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writel((cs->size - 1) & 0xffff0000,
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priv->reg + MVNETA_WIN_SIZE(i));
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win_enable &= ~(1 << i);
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win_protect |= 3 << (2 * i);
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}
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writel(win_enable, priv->reg + MVNETA_BASE_ADDR_ENABLE);
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}
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static void mvneta_clear_mcast_table(struct mvneta_port *priv)
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{
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int offset;
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for (offset = 0; offset <= 0xfc; offset += 4) {
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writel(0, priv->reg + MVNETA_DA_FILT_UCAST_BASE + offset);
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writel(0, priv->reg + MVNETA_DA_FILT_SPEC_MCAST + offset);
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writel(0, priv->reg + MVNETA_DA_FILT_OTH_MCAST + offset);
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}
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}
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/* Set unicast address */
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static void mvneta_set_ucast_addr(struct mvneta_port *priv, u8 last_nibble)
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{
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unsigned int tbl_offset, reg_offset;
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int queue = 0;
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u32 val;
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/* Locate the Unicast table entry */
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last_nibble = (0xf & last_nibble);
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/* offset from unicast tbl base */
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tbl_offset = (last_nibble / 4) * 4;
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/* offset within the above reg */
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reg_offset = last_nibble % 4;
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val = readl(priv->reg + MVNETA_DA_FILT_UCAST_BASE + tbl_offset);
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val &= ~(0xff << (8 * reg_offset));
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val |= ((0x01 | (queue << 1)) << (8 * reg_offset));
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writel(val, priv->reg + MVNETA_DA_FILT_UCAST_BASE + tbl_offset);
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}
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static void mvneta_clear_ucast_addr(struct mvneta_port *priv, u8 last_nibble)
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{
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unsigned int tbl_offset, reg_offset;
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u32 val;
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/* Locate the Unicast table entry */
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last_nibble = (0xf & last_nibble);
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/* offset from unicast tbl base */
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tbl_offset = (last_nibble / 4) * 4;
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/* offset within the above reg */
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reg_offset = last_nibble % 4;
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val = readl(priv->reg + MVNETA_DA_FILT_UCAST_BASE + tbl_offset);
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/* Clear accepts frame bit at specified unicast DA tbl entry */
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val &= ~(0xff << (8 * reg_offset));
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writel(val, priv->reg + MVNETA_DA_FILT_UCAST_BASE + tbl_offset);
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}
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static void mvneta_rx_unicast_promisc_clear(struct mvneta_port *priv)
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{
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u32 portcfg, val;
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portcfg = readl(priv->reg + MVNETA_PORT_CONFIG);
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val = readl(priv->reg + MVNETA_TYPE_PRIO);
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/* Reject all Unicast addresses */
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writel(portcfg & ~BIT(0), priv->reg + MVNETA_PORT_CONFIG);
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writel(val & ~BIT(21), priv->reg + MVNETA_TYPE_PRIO);
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}
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/* Clear all MIB counters */
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static void mvneta_mib_counters_clear(struct mvneta_port *priv)
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{
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int i;
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/* Perform dummy reads from MIB counters */
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for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
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readl(priv->reg + MVNETA_MIB_COUNTERS_BASE + i);
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}
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static int mvneta_pending_tx(struct mvneta_port *priv)
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{
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u32 val = readl(priv->reg + MVNETA_TXQ_STATUS_REG(0));
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return val & 0x3fff;
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}
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static int mvneta_pending_rx(struct mvneta_port *priv)
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{
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u32 val = readl(priv->reg + MVNETA_RXQ_STATUS_REG(0));
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return val & 0x3fff;
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}
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static void mvneta_port_stop(struct mvneta_port *priv)
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{
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u32 val;
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/* Stop all queues */
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writel(0xff << MVNETA_RXQ_DISABLE_SHIFT, priv->reg + MVNETA_RXQ_CMD);
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writel(0xff << MVNETA_TXQ_DISABLE_SHIFT, priv->reg + MVNETA_TXQ_CMD);
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/* Reset Tx */
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writel(BIT(0), priv->reg + MVNETA_PORT_TX_RESET);
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writel(0, priv->reg + MVNETA_PORT_TX_RESET);
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/* Reset Rx */
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writel(BIT(0), priv->reg + MVNETA_PORT_RX_RESET);
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writel(0, priv->reg + MVNETA_PORT_RX_RESET);
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/* Disable port 0 */
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val = readl(priv->reg + MVNETA_GMAC_CTRL_0);
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writel(val & ~BIT(0), priv->reg + MVNETA_GMAC_CTRL_0);
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udelay(200);
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/* Clear all Cause registers */
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writel(0, priv->reg + MVNETA_INTR_NEW_CAUSE);
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writel(0, priv->reg + MVNETA_INTR_OLD_CAUSE);
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writel(0, priv->reg + MVNETA_INTR_MISC_CAUSE);
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writel(0, priv->reg + MVNETA_UNIT_INTR_CAUSE);
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/* Mask all interrupts */
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writel(0, priv->reg + MVNETA_INTR_NEW_MASK);
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writel(0, priv->reg + MVNETA_INTR_OLD_MASK);
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writel(0, priv->reg + MVNETA_INTR_MISC_MASK);
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writel(0, priv->reg + MVNETA_INTR_ENABLE);
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}
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static void mvneta_halt(struct eth_device *edev)
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{
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mvneta_port_stop((struct mvneta_port *)edev->priv);
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}
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static int mvneta_send(struct eth_device *edev, void *data, int len)
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{
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struct mvneta_port *priv = edev->priv;
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struct txdesc *txdesc = priv->txdesc;
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int ret, error, last_desc;
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/* Flush transmit data */
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dma_sync_single_for_device((unsigned long)data, len, DMA_TO_DEVICE);
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/* Fill the Tx descriptor */
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txdesc->cmd_sts |= MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
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txdesc->buf_ptr = (u32)data;
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txdesc->byte_cnt = len;
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/* Increase the number of prepared descriptors (one), by writing
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* to the 'NoOfWrittenDescriptors' field in the PTXSU register.
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*/
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writel(1, priv->reg + MVNETA_TXQ_UPDATE_REG(0));
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/* The controller updates the number of transmitted descriptors in
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* the Tx port status register (PTXS).
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*/
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ret = wait_on_timeout(TRANSFER_TIMEOUT, !mvneta_pending_tx(priv));
|
|
dma_sync_single_for_cpu((unsigned long)data, len, DMA_TO_DEVICE);
|
|
if (ret) {
|
|
dev_err(&edev->dev, "transmit timeout\n");
|
|
return ret;
|
|
}
|
|
|
|
last_desc = readl(&txdesc->cmd_sts) & MVNETA_TXD_L_DESC;
|
|
error = readl(&txdesc->error);
|
|
if (last_desc && error & MVNETA_TXD_ERROR) {
|
|
dev_err(&edev->dev, "transmit error %d\n",
|
|
(error & TXD_ERROR_MASK) >> TXD_ERROR_SHIFT);
|
|
return -EIO;
|
|
}
|
|
|
|
/* Release the transmitted descriptor by writing to the
|
|
* 'NoOfReleasedBuffers' field in the PTXSU register.
|
|
*/
|
|
writel(1 << MVNETA_TXQ_DEC_SENT_SHIFT,
|
|
priv->reg + MVNETA_TXQ_UPDATE_REG(0));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvneta_recv(struct eth_device *edev)
|
|
{
|
|
struct mvneta_port *priv = edev->priv;
|
|
struct rxdesc *rxdesc = &priv->rxdesc[priv->curr_rxdesc];
|
|
int ret, pending;
|
|
u32 cmd_sts;
|
|
|
|
/* wait for received packet */
|
|
pending = mvneta_pending_rx(priv);
|
|
if (!pending)
|
|
return 0;
|
|
|
|
/* drop malicious packets */
|
|
cmd_sts = readl(&rxdesc->cmd_sts);
|
|
if ((cmd_sts & MVNETA_RXD_FIRST_LAST_DESC) !=
|
|
MVNETA_RXD_FIRST_LAST_DESC) {
|
|
dev_err(&edev->dev, "rx packet spread on multiple descriptors\n");
|
|
ret = -EIO;
|
|
goto recv_err;
|
|
}
|
|
|
|
if (cmd_sts & MVNETA_RXD_ERR_SUMMARY) {
|
|
dev_err(&edev->dev, "receive error\n");
|
|
ret = -EIO;
|
|
goto recv_err;
|
|
}
|
|
|
|
/* invalidate current receive buffer */
|
|
dma_sync_single_for_cpu((unsigned long)rxdesc->buf_phys_addr,
|
|
ALIGN(PKTSIZE, 8), DMA_FROM_DEVICE);
|
|
|
|
/* received packet is padded with two null bytes (Marvell header) */
|
|
net_receive(edev, (void *)(rxdesc->buf_phys_addr + MVNETA_MH_SIZE),
|
|
rxdesc->data_size - MVNETA_MH_SIZE);
|
|
ret = 0;
|
|
|
|
dma_sync_single_for_device((unsigned long)rxdesc->buf_phys_addr,
|
|
ALIGN(PKTSIZE, 8), DMA_FROM_DEVICE);
|
|
|
|
recv_err:
|
|
/* reset this and get next rx descriptor*/
|
|
rxdesc->data_size = 0;
|
|
rxdesc->cmd_sts = 0;
|
|
|
|
priv->curr_rxdesc++;
|
|
if (priv->curr_rxdesc == RX_RING_SIZE)
|
|
priv->curr_rxdesc = 0;
|
|
|
|
/* Descriptor processed and refilled */
|
|
writel(1 | 1 << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT,
|
|
priv->reg + MVNETA_RXQ_STATUS_UPDATE_REG(0));
|
|
return ret;
|
|
}
|
|
|
|
static int mvneta_set_ethaddr(struct eth_device *edev, unsigned char *mac)
|
|
{
|
|
struct mvneta_port *priv = edev->priv;
|
|
u32 mac_h = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
|
|
u32 mac_l = (mac[4] << 8) | mac[5];
|
|
|
|
mvneta_clear_ucast_addr(priv, mac[5]);
|
|
|
|
writel(mac_l, priv->reg + MVNETA_MAC_ADDR_LOW);
|
|
writel(mac_h, priv->reg + MVNETA_MAC_ADDR_HIGH);
|
|
|
|
/* accept frames for this address */
|
|
mvneta_set_ucast_addr(priv, mac[5]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvneta_get_ethaddr(struct eth_device *edev, unsigned char *mac)
|
|
{
|
|
struct mvneta_port *priv = edev->priv;
|
|
u32 mac_l = readl(priv->reg + MVNETA_MAC_ADDR_LOW);
|
|
u32 mac_h = readl(priv->reg + MVNETA_MAC_ADDR_HIGH);
|
|
|
|
mac[0] = (mac_h >> 24) & 0xff;
|
|
mac[1] = (mac_h >> 16) & 0xff;
|
|
mac[2] = (mac_h >> 8) & 0xff;
|
|
mac[3] = mac_h & 0xff;
|
|
mac[4] = (mac_l >> 8) & 0xff;
|
|
mac[5] = mac_l & 0xff;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mvneta_adjust_link(struct eth_device *edev)
|
|
{
|
|
struct mvneta_port *priv = edev->priv;
|
|
struct phy_device *phy = edev->phydev;
|
|
u32 val;
|
|
|
|
if (!phy->link)
|
|
return;
|
|
|
|
val = readl(priv->reg + MVNETA_GMAC_AUTONEG_CONFIG);
|
|
val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
|
|
MVNETA_GMAC_CONFIG_GMII_SPEED |
|
|
MVNETA_GMAC_CONFIG_FULL_DUPLEX |
|
|
MVNETA_GMAC_AN_SPEED_EN |
|
|
MVNETA_GMAC_AN_FLOWCTRL_EN |
|
|
MVNETA_GMAC_AN_DUPLEX_EN);
|
|
|
|
if (phy->speed == SPEED_1000)
|
|
val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
|
|
else if (phy->speed == SPEED_100)
|
|
val |= MVNETA_GMAC_CONFIG_MII_SPEED;
|
|
|
|
if (phy->duplex)
|
|
val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
|
|
|
if (phy->pause)
|
|
val |= MVNETA_GMAC_CONFIG_FLOWCTRL;
|
|
|
|
val |= MVNETA_GMAC_FORCE_LINK_PASS | MVNETA_GMAC_FORCE_LINK_DOWN;
|
|
|
|
writel(val, priv->reg + MVNETA_GMAC_AUTONEG_CONFIG);
|
|
|
|
mvneta_mib_counters_clear(priv);
|
|
|
|
/* Enable first Tx and first Rx queues */
|
|
writel(BIT(0), priv->reg + MVNETA_TXQ_CMD);
|
|
writel(BIT(0), priv->reg + MVNETA_RXQ_CMD);
|
|
}
|
|
|
|
static int mvneta_open(struct eth_device *edev)
|
|
{
|
|
struct mvneta_port *priv = edev->priv;
|
|
int ret;
|
|
u32 val;
|
|
|
|
ret = phy_device_connect(&priv->edev, NULL, -1,
|
|
mvneta_adjust_link, 0, priv->intf);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable the first port */
|
|
val = readl(priv->reg + MVNETA_GMAC_CTRL_0);
|
|
writel(val | BIT(0), priv->reg + MVNETA_GMAC_CTRL_0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mvneta_init_rx_ring(struct mvneta_port *priv)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < RX_RING_SIZE; i++) {
|
|
struct rxdesc *desc = &priv->rxdesc[i];
|
|
|
|
desc->buf_phys_addr = (u32)priv->rxbuf + i * ALIGN(PKTSIZE, 8);
|
|
}
|
|
|
|
priv->curr_rxdesc = 0;
|
|
}
|
|
|
|
void mvneta_setup_tx_rx(struct mvneta_port *priv)
|
|
{
|
|
u32 val;
|
|
|
|
/* Allocate descriptors and buffers */
|
|
priv->txdesc = dma_alloc_coherent(ALIGN(sizeof(*priv->txdesc), 32),
|
|
DMA_ADDRESS_BROKEN);
|
|
priv->rxdesc = dma_alloc_coherent(RX_RING_SIZE *
|
|
ALIGN(sizeof(*priv->rxdesc), 32),
|
|
DMA_ADDRESS_BROKEN);
|
|
priv->rxbuf = dma_alloc(RX_RING_SIZE * ALIGN(PKTSIZE, 8));
|
|
|
|
mvneta_init_rx_ring(priv);
|
|
|
|
/* Configure the Rx queue */
|
|
val = readl(priv->reg + MVNETA_RXQ_CONFIG_REG(0));
|
|
val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
|
|
writel(val, priv->reg + MVNETA_RXQ_CONFIG_REG(0));
|
|
|
|
/* Configure the Tx descriptor */
|
|
writel(1, priv->reg + MVNETA_TXQ_SIZE_REG(0));
|
|
writel((u32)priv->txdesc, priv->reg + MVNETA_TXQ_BASE_ADDR_REG(0));
|
|
|
|
/* Configure the Rx descriptor. Packet size is in 8-byte units. */
|
|
val = RX_RING_SIZE;
|
|
val |= ((PKTSIZE >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
|
|
writel(val , priv->reg + MVNETA_RXQ_SIZE_REG(0));
|
|
writel((u32)priv->rxdesc, priv->reg + MVNETA_RXQ_BASE_ADDR_REG(0));
|
|
|
|
/* Set the number of available Rx descriptors */
|
|
writel(RX_RING_SIZE << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT,
|
|
priv->reg + MVNETA_RXQ_STATUS_UPDATE_REG(0));
|
|
}
|
|
|
|
static int mvneta_port_config(struct mvneta_port *priv)
|
|
{
|
|
int queue;
|
|
u32 val;
|
|
|
|
/* Enable MBUS Retry bit16 */
|
|
writel(0x20, priv->reg + MVNETA_MBUS_RETRY);
|
|
|
|
/* Map the first Tx queue and first Rx queue to CPU0 */
|
|
writel(BIT(0) | (BIT(0) << 8), priv->reg + MVNETA_CPU_MAP(0));
|
|
|
|
/* Reset Tx/Rx DMA */
|
|
writel(BIT(0), priv->reg + MVNETA_PORT_TX_RESET);
|
|
writel(BIT(0), priv->reg + MVNETA_PORT_RX_RESET);
|
|
|
|
/* Disable Legacy WRR, Disable EJP, Release from reset */
|
|
writel(0, priv->reg + MVNETA_TXQ_CMD_1);
|
|
|
|
/* Set maximum bandwidth for the first TX queue */
|
|
writel(0x3ffffff, priv->reg + MVETH_TXQ_TOKEN_CFG_REG(0));
|
|
writel(0x3ffffff, priv->reg + MVETH_TXQ_TOKEN_COUNT_REG(0));
|
|
|
|
/* Minimum bandwidth on the rest of them */
|
|
for (queue = 1; queue < TXQ_NUM; queue++) {
|
|
writel(0, priv->reg + MVETH_TXQ_TOKEN_COUNT_REG(queue));
|
|
writel(0, priv->reg + MVETH_TXQ_TOKEN_CFG_REG(queue));
|
|
}
|
|
|
|
writel(0, priv->reg + MVNETA_PORT_RX_RESET);
|
|
writel(0, priv->reg + MVNETA_PORT_TX_RESET);
|
|
|
|
/* Disable hardware PHY polling */
|
|
val = readl(priv->reg + MVNETA_UNIT_CONTROL);
|
|
writel(val & ~BIT(1), priv->reg + MVNETA_UNIT_CONTROL);
|
|
|
|
/* Port Acceleration Mode */
|
|
writel(0x1, priv->reg + MVNETA_ACC_MODE);
|
|
|
|
/* Port default configuration for the first Rx queue */
|
|
val = MVNETA_PORT_CONFIG_DEFL_VALUE(0);
|
|
writel(val, priv->reg + MVNETA_PORT_CONFIG);
|
|
writel(0, priv->reg + MVNETA_PORT_CONFIG_EXTEND);
|
|
writel(64, priv->reg + MVNETA_RX_MIN_FRAME_SIZE);
|
|
|
|
/* Default burst size */
|
|
val = 0;
|
|
val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
|
|
val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
|
|
val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
|
|
writel(val, priv->reg + MVNETA_SDMA_CONFIG);
|
|
|
|
mvneta_clear_mcast_table(priv);
|
|
mvneta_rx_unicast_promisc_clear(priv);
|
|
|
|
/* Configure maximum MTU and token size */
|
|
writel(0x0003ffff, priv->reg + MVNETA_TX_MTU);
|
|
writel(0xffffffff, priv->reg + MVNETA_TX_TOKEN_SIZE);
|
|
writel(0x7fffffff, priv->reg + MVNETA_TXQ_TOKEN_SIZE_REG(0));
|
|
|
|
val = readl(priv->reg + MVNETA_GMAC_CTRL_2);
|
|
|
|
/* Even though it might look weird, when we're configured in
|
|
* SGMII or QSGMII mode, the RGMII bit needs to be set.
|
|
*/
|
|
switch (priv->intf) {
|
|
case PHY_INTERFACE_MODE_QSGMII:
|
|
writel(MVNETA_QSGMII_SERDES, priv->reg + MVNETA_SERDES_CFG);
|
|
val |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
|
|
break;
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
writel(MVNETA_SGMII_SERDES, priv->reg + MVNETA_SERDES_CFG);
|
|
val |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
|
|
break;
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
val |= MVNETA_GMAC2_PORT_RGMII;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Cancel Port Reset */
|
|
val &= ~MVNETA_GMAC2_PORT_RESET;
|
|
writel(val, priv->reg + MVNETA_GMAC_CTRL_2);
|
|
while (readl(priv->reg + MVNETA_GMAC_CTRL_2) & MVNETA_GMAC2_PORT_RESET)
|
|
continue;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mvneta_probe(struct device_d *dev)
|
|
{
|
|
struct mvneta_port *priv;
|
|
int ret;
|
|
|
|
priv = xzalloc(sizeof(*priv));
|
|
|
|
priv->reg = dev_get_mem_region(dev, 0);
|
|
|
|
priv->clk = clk_get(dev, 0);
|
|
if (IS_ERR(priv->clk))
|
|
return PTR_ERR(priv->clk);
|
|
clk_enable(priv->clk);
|
|
|
|
ret = of_get_phy_mode(dev->device_node);
|
|
if (ret < 0)
|
|
return ret;
|
|
priv->intf = ret;
|
|
|
|
mvneta_port_stop(priv);
|
|
|
|
ret = mvneta_port_config(priv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mvneta_conf_mbus_windows(priv);
|
|
mvneta_setup_tx_rx(priv);
|
|
|
|
/* register eth device */
|
|
priv->edev.priv = priv;
|
|
priv->edev.open = mvneta_open;
|
|
priv->edev.send = mvneta_send;
|
|
priv->edev.recv = mvneta_recv;
|
|
priv->edev.halt = mvneta_halt;
|
|
priv->edev.set_ethaddr = mvneta_set_ethaddr;
|
|
priv->edev.get_ethaddr = mvneta_get_ethaddr;
|
|
priv->edev.parent = dev;
|
|
|
|
ret = eth_register(&priv->edev);
|
|
if (ret)
|
|
return ret;
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id mvneta_dt_ids[] = {
|
|
{ .compatible = "marvell,armada-370-neta", },
|
|
{ }
|
|
};
|
|
|
|
static struct driver_d mvneta_driver = {
|
|
.name = "mvneta",
|
|
.probe = mvneta_probe,
|
|
.of_compatible = DRV_OF_COMPAT(mvneta_dt_ids),
|
|
};
|
|
device_platform_driver(mvneta_driver);
|