563 lines
14 KiB
C
563 lines
14 KiB
C
/*
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* (C) Copyright 2014
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* Pengutronix, Michael Grzeschik <mgr@pengutronix.de>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on kirkwood_egiga driver from u-boot
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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*
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* based on - Driver for MV64360X ethernet ports
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* Copyright (C) 2002 rabeeh@galileo.co.il
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <dma.h>
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#include <init.h>
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#include <io.h>
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#include <net.h>
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#include <of_net.h>
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#include <linux/sizes.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mbus.h>
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#include "orion-gbe.h"
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struct rxdesc {
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u32 cmd_sts; /* Descriptor command status */
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u16 buf_size; /* Buffer size */
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u16 byte_cnt; /* Descriptor buffer byte count */
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void *buf_ptr; /* Descriptor buffer pointer */
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struct rxdesc *nxtdesc; /* Next descriptor pointer */
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};
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struct txdesc {
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u32 cmd_sts; /* Descriptor command status */
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u16 l4i_chk; /* CPU provided TCP Checksum */
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u16 byte_cnt; /* Descriptor buffer byte count */
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void *buf_ptr; /* Descriptor buffer ptr */
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struct txdesc *nxtdesc; /* Next descriptor ptr */
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};
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struct port_priv {
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struct device_d dev;
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struct eth_device edev;
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void __iomem *regs;
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struct device_node *np;
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int portno;
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struct txdesc *txdesc;
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struct rxdesc *rxdesc;
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struct rxdesc *current_rxdesc;
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u8 *rxbuf;
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phy_interface_t intf;
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};
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struct orion_gbe {
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void __iomem *regs;
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struct clk *clk;
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struct port_priv *ports;
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int num_ports;
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};
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#define UTXQ 0 /* Used Tx queue number */
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#define URXQ 0 /* Used Rx queue number */
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#define RX_RING_SIZE 4
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#define TRANSFER_TIMEOUT (10 * MSECOND)
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#define NR_ADDR_WINS 6 /* number of address windows */
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#define NR_HIGH_ADDR_WINS 4 /* number of high address windows */
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#define ACCEPT_MAC_ADDR 0
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#define REJECT_MAC_ADDR 1
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/* setup DRAM access windows provided by mbus */
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static void eunit_set_dram_access(struct orion_gbe *gbe)
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{
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const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
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u32 bare = ~0, epap = 0, reg;
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int n;
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for (n = 0; n < NR_ADDR_WINS; n++) {
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if (n >= dram->num_cs)
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continue;
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/* enable BAR */
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bare &= ~BIT(n);
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/* set port access protect to R/W */
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epap |= ACCESS_FULL << (n * 2);
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/* configure Base Address and Size */
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reg = ((dram->cs[n].size / SZ_64K) - 1) << 16;
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writel(reg, gbe->regs + EUNIT_S(n));
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reg = dram->cs[n].base & 0xffff0000;
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reg |= dram->cs[n].mbus_attr << 8;
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reg |= dram->mbus_dram_target_id;
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writel(reg, gbe->regs + EUNIT_BA(n));
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if (n < NR_HIGH_ADDR_WINS)
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writel(0, gbe->regs + EUNIT_HA(n));
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}
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writel(epap, gbe->regs + EUNIT_PAP);
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writel(bare, gbe->regs + EUNIT_BARE);
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}
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/* clear entries in unicast, special multicast, and other multicast tables */
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static void port_clear_mac_tables(struct port_priv *port)
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{
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int n;
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/* clear unicast tables (DFUTn) */
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for (n = 0; n < 4; n++)
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writel(0, port->regs + PORT_DFUT(n));
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/* clear special (DFSMTn) and other (DFOMTn) multicast tables */
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for (n = 0; n < 64; n++) {
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writel(0, port->regs + PORT_DFSMT(n));
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writel(0, port->regs + PORT_DFOMT(n));
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}
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}
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/*
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* set the port unicast address table
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*
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* This function adds/removes MAC addresses from the port unicast
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* address table.
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*
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* Locate the proper entry in the Unicast table for the specified MAC
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* nibble and set its properties according to function parameters.
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*
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* @nibble Unicast MAC address, last nibble
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* @reject 0 = Accept, 1 = Reject MAC address
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*/
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static void port_set_unicast_filter(struct port_priv *port,
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u8 nibble, int reject)
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{
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u8 table, entry, shift;
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u32 reg;
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/* Locate the Unicast table entry by nibble */
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nibble &= 0xf;
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table = nibble / 4;
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entry = nibble % 4;
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shift = (DFT_ENTRY_SIZE * entry);
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reg = readl(port->regs + PORT_DFUT(table));
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reg &= DFT_ENTRY_MASK << shift;
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if (!reject)
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reg |= (DFT_PASS | (URXQ << DFT_QUEUE_SHIFT)) << shift;
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writel(reg, port->regs + PORT_DFUT(table));
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}
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/* initialize rx descriptor ring */
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static void port_init_rxdesc_ring(struct port_priv *port)
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{
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struct rxdesc *rxdesc, *nxtdesc;
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void *rxbuf;
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int n;
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/* initialize aligned rx descriptor ring-buffer */
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rxdesc = port->rxdesc;
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rxbuf = port->rxbuf;
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for (n = 0; n < RX_RING_SIZE; n++) {
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nxtdesc = ((void *)rxdesc) + ALIGN(sizeof(*port->rxdesc), 16);
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rxdesc->cmd_sts = RXDESC_OWNED_BY_DMA;
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rxdesc->buf_size = ALIGN(PKTSIZE, 8);
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rxdesc->byte_cnt = 0;
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rxdesc->buf_ptr = rxbuf;
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if (n == RX_RING_SIZE-1)
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rxdesc->nxtdesc = port->rxdesc;
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else
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rxdesc->nxtdesc = nxtdesc;
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rxbuf += ALIGN(PKTSIZE, 8);
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rxdesc = nxtdesc;
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}
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port->current_rxdesc = port->rxdesc;
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}
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/* stop a queue and check for termination */
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static void port_stop_queue(void __iomem *ctrl)
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{
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u32 reg = readl(ctrl);
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if (!(reg & 0xff))
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return;
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/* stop active channels only */
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writel((reg << 8), ctrl);
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/* wait for all queues to terminate */
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while (readl(ctrl) & 0xff)
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;
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}
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static void port_stop(struct port_priv *port)
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{
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/* stop all queues */
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port_stop_queue(port->regs + PORT_TQC);
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port_stop_queue(port->regs + PORT_RQC);
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/* disable port, release reset */
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writel(readl(port->regs + PORT_SC0) & ~PORT_ENABLE,
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port->regs + PORT_SC0);
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writel(readl(port->regs + PORT_SC1) & ~PORT_RESET,
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port->regs + PORT_SC1);
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/* clear and mask all interrupts */
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writel(0, port->regs + PORT_IC);
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writel(0, port->regs + PORT_IM);
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writel(0, port->regs + PORT_EIC);
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writel(0, port->regs + PORT_EIM);
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}
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static void port_halt(struct eth_device *edev)
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{
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struct port_priv *port = edev->priv;
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port_stop(port);
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}
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static int port_send(struct eth_device *edev, void *data, int len)
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{
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struct port_priv *port = edev->priv;
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struct txdesc *txdesc = port->txdesc;
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u32 cmd_sts;
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int ret;
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/* flush transmit data */
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dma_sync_single_for_device((unsigned long)data, len, DMA_TO_DEVICE);
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txdesc->cmd_sts = TXDESC_OWNED_BY_DMA;
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txdesc->cmd_sts |= TXDESC_FIRST | TXDESC_LAST;
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txdesc->cmd_sts |= TXDESC_ZERO_PADDING | TXDESC_GEN_CRC;
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txdesc->buf_ptr = data;
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txdesc->byte_cnt = len;
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/* assign tx descriptor and issue send command */
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writel((u32)txdesc, port->regs + PORT_TCQDP(UTXQ));
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writel(BIT(UTXQ), port->regs + PORT_TQC);
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/* wait for packet transmit completion */
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ret = wait_on_timeout(TRANSFER_TIMEOUT,
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(readl(&txdesc->cmd_sts) & TXDESC_OWNED_BY_DMA) == 0);
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dma_sync_single_for_cpu((unsigned long)data, len, DMA_TO_DEVICE);
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if (ret) {
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dev_err(&edev->dev, "transmit timeout\n");
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return ret;
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}
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cmd_sts = readl(&txdesc->cmd_sts);
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if ((cmd_sts & TXDESC_LAST) && (cmd_sts & TXDESC_ERROR)) {
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dev_err(&edev->dev, "transmit error %d\n",
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(cmd_sts & TXDESC_ERROR_MASK) >> TXDESC_ERROR_SHIFT);
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return ret;
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}
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return 0;
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}
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static int port_recv(struct eth_device *edev)
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{
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struct port_priv *port = edev->priv;
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struct rxdesc *rxdesc = port->current_rxdesc;
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u32 cmd_sts;
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int ret = 0;
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/* wait for received packet */
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if (readl(&rxdesc->cmd_sts) & RXDESC_OWNED_BY_DMA)
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return 0;
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/* drop malicious packets */
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cmd_sts = readl(&rxdesc->cmd_sts);
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if ((cmd_sts & (RXDESC_FIRST | RXDESC_LAST)) !=
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(RXDESC_FIRST | RXDESC_LAST)) {
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dev_err(&edev->dev, "rx packet spread on multiple descriptors\n");
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ret = -EIO;
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goto recv_err;
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}
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if (cmd_sts & RXDESC_ERROR) {
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dev_err(&edev->dev, "receive error %d\n",
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(cmd_sts & RXDESC_ERROR_MASK) >> RXDESC_ERROR_SHIFT);
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ret = -EIO;
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goto recv_err;
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}
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/* invalidate current receive buffer */
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dma_sync_single_for_cpu((unsigned long)rxdesc->buf_ptr,
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ALIGN(PKTSIZE, 8), DMA_FROM_DEVICE);
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/* received packet is padded with two null bytes */
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net_receive(edev, rxdesc->buf_ptr + 0x2, rxdesc->byte_cnt - 0x2);
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dma_sync_single_for_device((unsigned long)rxdesc->buf_ptr,
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ALIGN(PKTSIZE, 8), DMA_FROM_DEVICE);
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ret = 0;
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recv_err:
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/* reset this and get next rx descriptor*/
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rxdesc->byte_cnt = 0;
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rxdesc->buf_size = ALIGN(PKTSIZE, 8);
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rxdesc->cmd_sts = RXDESC_OWNED_BY_DMA;
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writel((u32)rxdesc->nxtdesc, &port->current_rxdesc);
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return ret;
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}
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static int port_set_ethaddr(struct eth_device *edev, unsigned char *mac)
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{
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struct port_priv *port = edev->priv;
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u32 mac_h = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
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u32 mac_l = (mac[4] << 8) | mac[5];
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port_clear_mac_tables(port);
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writel(mac_l, port->regs + PORT_MACAL);
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writel(mac_h, port->regs + PORT_MACAH);
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/* accept frames for this address */
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port_set_unicast_filter(port, mac[5], ACCEPT_MAC_ADDR);
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return 0;
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}
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static int port_get_ethaddr(struct eth_device *edev, unsigned char *mac)
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{
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struct port_priv *port = edev->priv;
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u32 reg;
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reg = readl(port->regs + PORT_MACAH);
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mac[0] = (u8)(reg >> 24) & 0xff;
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mac[1] = (u8)(reg >> 16) & 0xff;
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mac[2] = (u8)(reg >> 8) & 0xff;
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mac[3] = (u8)reg & 0xff;
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reg = readl(port->regs + PORT_MACAL);
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mac[4] = (u8)(reg >> 8) & 0xff;
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mac[5] = (u8)reg & 0xff;
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return 0;
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}
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static void port_adjust_link(struct eth_device *edev)
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{
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struct port_priv *port = edev->priv;
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struct phy_device *phy = edev->phydev;
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u32 reg;
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/* disable port */
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reg = readl(port->regs + PORT_SC0);
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reg &= ~PORT_ENABLE;
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writel(reg, port->regs + PORT_SC0);
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/* setup and enable port */
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reg &= ~(SET_SPEED_MASK | SET_FULL_DUPLEX | SET_FLOWCTRL_ENABLE);
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if (phy->speed == SPEED_1000)
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reg |= SET_SPEED_1000;
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else if (phy->speed == SPEED_100)
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reg |= SET_SPEED_100;
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else if (phy->speed == SPEED_10)
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reg |= SET_SPEED_10;
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if (phy->duplex)
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reg |= SET_FULL_DUPLEX;
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if (phy->pause)
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reg |= SET_FLOWCTRL_ENABLE;
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reg |= FORCE_LINK_PASS | FORCE_NO_LINK_FAIL | PORT_ENABLE;
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writel(reg, port->regs + PORT_SC0);
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}
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static int port_open(struct eth_device *edev)
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{
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struct port_priv *port = edev->priv;
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int ret;
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ret = phy_device_connect(&port->edev, NULL, -1, port_adjust_link, 0,
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port->intf);
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if (ret)
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return ret;
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/* enable receive queue */
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writel(BIT(URXQ), port->regs + PORT_RQC);
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return 0;
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}
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static int port_probe(struct device_d *parent, struct port_priv *port)
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{
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struct orion_gbe *gbe = parent->priv;
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struct device_d *dev = &port->dev;
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u32 reg;
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int ret;
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/* assume port0 but warn on missing port reg property */
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if (of_property_read_u32(port->np, "reg", &port->portno))
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dev_warn(parent, "port node is missing reg property\n");
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ret = of_get_phy_mode(port->np);
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if (ret > 0)
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port->intf = ret;
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else
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port->intf = PHY_INTERFACE_MODE_RGMII;
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port->regs = dev_get_mem_region(parent, 0) + PORTn_REGS(port->portno);
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if (IS_ERR(port->regs))
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return PTR_ERR(port->regs);
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/* allocate rx/tx descriptors and buffers */
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port->txdesc = dma_alloc_coherent(ALIGN(sizeof(*port->txdesc), 16),
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DMA_ADDRESS_BROKEN);
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port->rxdesc = dma_alloc_coherent(RX_RING_SIZE *
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ALIGN(sizeof(*port->rxdesc), 16),
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DMA_ADDRESS_BROKEN);
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port->rxbuf = dma_alloc(RX_RING_SIZE * ALIGN(PKTSIZE, 8));
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port_stop(port);
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port_init_rxdesc_ring(port);
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/* disable port bandwidth limitation */
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writel(~0, port->regs + PORT_TQTBCNT(UTXQ));
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writel(~0, port->regs + PORT_TQTBC(UTXQ));
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writel(0, port->regs + PORT_MTU);
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/* assign initial rx descriptor */
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writel((u32)port->current_rxdesc, port->regs + PORT_CRDP(URXQ));
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/* setup SDMA with maximum burst and no swap */
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reg = RX_BURST_SIZE_16 | RX_BLM_NO_SWAP |
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TX_BURST_SIZE_16 | TX_BLM_NO_SWAP;
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writel(reg, port->regs + PORT_SDC);
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/* port configuration */
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reg = DEFAULT_RXQ(URXQ) | DEFAULT_ARPQ(URXQ);
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writel(reg, port->regs + PORT_C);
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writel(0, port->regs + PORT_CX);
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reg = SC0_RESERVED | MRU_1518;
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reg |= DISABLE_ANEG_DUPLEX | DISABLE_ANEG_FLOWCTRL | DISABLE_ANEG_SPEED;
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writel(reg, port->regs + PORT_SC0);
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reg = SC1_RESERVED;
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reg |= DEFAULT_COL_LIMIT | COL_ON_BACKPRESS | INBAND_ANEG_BYPASS;
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if (port->intf == PHY_INTERFACE_MODE_RGMII ||
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port->intf == PHY_INTERFACE_MODE_RGMII_ID ||
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port->intf == PHY_INTERFACE_MODE_RGMII_RXID ||
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port->intf == PHY_INTERFACE_MODE_RGMII_TXID)
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reg |= RGMII_ENABLE;
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writel(reg, port->regs + PORT_SC1);
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snprintf(dev->name, MAX_DRIVER_NAME, "%08x.ethernet-port", (u32)gbe->regs);
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dev->id = port->portno;
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dev->parent = parent;
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dev->device_node = port->np;
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ret = register_device(dev);
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if (ret)
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return ret;
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/* register eth device */
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port->edev.priv = port;
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port->edev.open = port_open;
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port->edev.send = port_send;
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port->edev.recv = port_recv;
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port->edev.halt = port_halt;
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port->edev.set_ethaddr = port_set_ethaddr;
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port->edev.get_ethaddr = port_get_ethaddr;
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port->edev.parent = dev;
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ret = eth_register(&port->edev);
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if (ret)
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return ret;
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return 0;
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}
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static int orion_gbe_probe(struct device_d *dev)
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{
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struct orion_gbe *gbe;
|
|
struct port_priv *ppriv;
|
|
struct device_node *pnp;
|
|
int ret;
|
|
|
|
gbe = xzalloc(sizeof(*gbe));
|
|
dev->priv = gbe;
|
|
|
|
gbe->regs = dev_get_mem_region(dev, 0);
|
|
if (IS_ERR(gbe->regs))
|
|
return PTR_ERR(gbe->regs);
|
|
|
|
gbe->clk = clk_get(dev, 0);
|
|
if (!IS_ERR(gbe->clk))
|
|
clk_enable(gbe->clk);
|
|
|
|
eunit_set_dram_access(gbe);
|
|
|
|
/*
|
|
* Orion SoCs only have one port per controller, but the
|
|
* IP itself supports more than one port per controller.
|
|
* Although untested, the driver should also be able to
|
|
* deal with multi-port controllers.
|
|
*/
|
|
for_each_child_of_node(dev->device_node, pnp)
|
|
gbe->num_ports++;
|
|
|
|
gbe->ports = xzalloc(gbe->num_ports * sizeof(*gbe->ports));
|
|
|
|
ppriv = gbe->ports;
|
|
for_each_child_of_node(dev->device_node, pnp) {
|
|
ppriv->np = pnp;
|
|
|
|
ret = port_probe(dev, ppriv);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ppriv++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void orion_gbe_remove(struct device_d *dev)
|
|
{
|
|
struct orion_gbe *gbe = dev->priv;
|
|
int n;
|
|
|
|
for (n = 0; n < gbe->num_ports; n++)
|
|
port_halt(&gbe->ports[n].edev);
|
|
|
|
/* disable all address windows */
|
|
writel(~0, gbe->regs + EUNIT_BARE);
|
|
|
|
if (!IS_ERR(gbe->clk))
|
|
clk_disable(gbe->clk);
|
|
}
|
|
|
|
static struct of_device_id orion_gbe_dt_ids[] = {
|
|
{ .compatible = "marvell,orion-eth", },
|
|
{ .compatible = "marvell,kirkwood-eth", },
|
|
{ }
|
|
};
|
|
|
|
static struct driver_d orion_gbe_driver = {
|
|
.name = "orion-gbe",
|
|
.probe = orion_gbe_probe,
|
|
.remove = orion_gbe_remove,
|
|
.of_compatible = DRV_OF_COMPAT(orion_gbe_dt_ids),
|
|
};
|
|
device_platform_driver(orion_gbe_driver);
|