699 lines
18 KiB
C
699 lines
18 KiB
C
/*
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* Copyright (C) 2005 HP Labs
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* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2014 Raphaël Poggi
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <complete.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <errno.h>
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#include <io.h>
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#include <gpio.h>
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#include <init.h>
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#include <driver.h>
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#include <getopt.h>
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#include <mach/at91_pio.h>
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#include <mach/gpio.h>
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#include <pinctrl.h>
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struct at91_pinctrl {
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struct pinctrl_device pctl;
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struct at91_pinctrl_mux_ops *ops;
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};
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struct at91_gpio_chip {
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struct gpio_chip chip;
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void __iomem *regbase; /* PIO bank virtual address */
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struct at91_pinctrl_mux_ops *ops; /* ops */
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};
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enum at91_mux {
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AT91_MUX_GPIO = 0,
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AT91_MUX_PERIPH_A = 1,
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AT91_MUX_PERIPH_B = 2,
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AT91_MUX_PERIPH_C = 3,
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AT91_MUX_PERIPH_D = 4,
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};
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#define MAX_GPIO_BANKS 5
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#define to_at91_pinctrl(c) container_of(c, struct at91_pinctrl, pctl);
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#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
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#define PULL_UP (1 << 0)
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#define MULTI_DRIVE (1 << 1)
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#define DEGLITCH (1 << 2)
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#define PULL_DOWN (1 << 3)
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#define DIS_SCHMIT (1 << 4)
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#define DEBOUNCE (1 << 16)
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#define DEBOUNCE_VAL_SHIFT 17
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#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
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static int gpio_banks;
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static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
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static inline struct at91_gpio_chip *pin_to_controller(unsigned pin)
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{
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pin /= MAX_NB_GPIO_PER_BANK;
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if (likely(pin < gpio_banks))
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return &gpio_chip[pin];
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return NULL;
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}
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/**
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* struct at91_pinctrl_mux_ops - describes an At91 mux ops group
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* on new IP with support for periph C and D the way to mux in
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* periph A and B has changed
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* So provide the right call back
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* if not present means the IP does not support it
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* @get_periph: return the periph mode configured
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* @mux_A_periph: mux as periph A
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* @mux_B_periph: mux as periph B
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* @mux_C_periph: mux as periph C
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* @mux_D_periph: mux as periph D
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* @set_deglitch: enable/disable deglitch
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* @set_debounce: enable/disable debounce
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* @set_pulldown: enable/disable pulldown
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* @disable_schmitt_trig: disable schmitt trigger
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*/
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struct at91_pinctrl_mux_ops {
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enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
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void (*mux_A_periph)(void __iomem *pio, unsigned mask);
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void (*mux_B_periph)(void __iomem *pio, unsigned mask);
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void (*mux_C_periph)(void __iomem *pio, unsigned mask);
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void (*mux_D_periph)(void __iomem *pio, unsigned mask);
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bool (*get_deglitch)(void __iomem *pio, unsigned pin);
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void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
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bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
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void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div);
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bool (*get_pulldown)(void __iomem *pio, unsigned pin);
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void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on);
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bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
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void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
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};
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int at91_mux_pin(unsigned pin, enum at91_mux mux, int use_pullup)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio;
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struct device_d *dev;
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unsigned mask = pin_to_mask(pin);
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int bank = pin_to_bank(pin);
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if (!at91_gpio)
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return -EINVAL;
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pio = at91_gpio->regbase;
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if (!pio)
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return -EINVAL;
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dev = at91_gpio->chip.dev;
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at91_mux_disable_interrupt(pio, mask);
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pin %= MAX_NB_GPIO_PER_BANK;
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if (mux) {
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dev_dbg(dev, "pio%c%d configured as periph%c with pullup = %d\n",
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bank + 'A', pin, mux - 1 + 'A', use_pullup);
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} else {
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dev_dbg(dev, "pio%c%d configured as gpio with pullup = %d\n",
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bank + 'A', pin, use_pullup);
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}
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switch(mux) {
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case AT91_MUX_GPIO:
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at91_mux_gpio_enable(pio, mask);
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break;
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case AT91_MUX_PERIPH_A:
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at91_gpio->ops->mux_A_periph(pio, mask);
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break;
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case AT91_MUX_PERIPH_B:
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at91_gpio->ops->mux_B_periph(pio, mask);
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break;
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case AT91_MUX_PERIPH_C:
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if (!at91_gpio->ops->mux_C_periph)
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return -EINVAL;
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at91_gpio->ops->mux_C_periph(pio, mask);
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break;
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case AT91_MUX_PERIPH_D:
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if (!at91_gpio->ops->mux_D_periph)
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return -EINVAL;
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at91_gpio->ops->mux_D_periph(pio, mask);
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break;
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}
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if (mux)
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at91_mux_gpio_disable(pio, mask);
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if (use_pullup >= 0)
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at91_mux_set_pullup(pio, mask, use_pullup);
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return 0;
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}
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EXPORT_SYMBOL(at91_mux_pin);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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int ret;
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ret = at91_mux_pin(pin, AT91_MUX_GPIO, use_pullup);
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if (ret)
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return ret;
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dev_dbg(at91_gpio->chip.dev, "pio%c%d configured as input\n",
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pin_to_bank(pin) + 'A', pin_to_bank_offset(pin));
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at91_mux_gpio_input(pio, mask, true);
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return 0;
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int at91_set_gpio_output(unsigned pin, int value)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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int ret;
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ret = at91_mux_pin(pin, AT91_MUX_GPIO, -1);
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if (ret)
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return ret;
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dev_dbg(at91_gpio->chip.dev, "pio%c%d configured as output val = %d\n",
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pin_to_bank(pin) + 'A', pin_to_bank_offset(pin), value);
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at91_mux_gpio_input(pio, mask, false);
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at91_mux_gpio_set(pio, mask, value);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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/*
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* enable/disable the glitch filter; mostly used with IRQ handling.
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*/
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int at91_set_deglitch(unsigned pin, int is_on)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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at91_gpio->ops->set_deglitch(pio, mask, is_on);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_deglitch);
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/*
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* enable/disable the debounce filter;
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*/
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int at91_set_debounce(unsigned pin, int is_on, int div)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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if (!pio || !at91_gpio->ops->set_debounce)
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return -EINVAL;
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at91_gpio->ops->set_debounce(pio, mask, is_on, div);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_debounce);
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/*
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* enable/disable the multi-driver; This is only valid for output and
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* allows the output pin to run as an open collector output.
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*/
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int at91_set_multi_drive(unsigned pin, int is_on)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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at91_mux_set_multidrive(pio, mask, is_on);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_multi_drive);
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/*
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* enable/disable the pull-down.
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* If pull-up already enabled while calling the function, we disable it.
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*/
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int at91_set_pulldown(unsigned pin, int is_on)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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if (!pio || !at91_gpio->ops->set_pulldown)
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return -EINVAL;
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/* Disable pull-up anyway */
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at91_mux_set_pullup(pio, mask, 0);
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at91_gpio->ops->set_pulldown(pio, mask, is_on);
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return 0;
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}
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EXPORT_SYMBOL(at91_set_pulldown);
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/*
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* disable Schmitt trigger
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*/
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int at91_disable_schmitt_trig(unsigned pin)
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{
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struct at91_gpio_chip *at91_gpio = pin_to_controller(pin);
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void __iomem *pio = at91_gpio->regbase;
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unsigned mask = pin_to_mask(pin);
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if (!pio || !at91_gpio->ops->disable_schmitt_trig)
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return -EINVAL;
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at91_gpio->ops->disable_schmitt_trig(pio, mask);
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return 0;
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}
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EXPORT_SYMBOL(at91_disable_schmitt_trig);
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static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask)
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{
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unsigned select;
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if (__raw_readl(pio + PIO_PSR) & mask)
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return AT91_MUX_GPIO;
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select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
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select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
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return select + 1;
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}
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static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
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{
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unsigned select;
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if (__raw_readl(pio + PIO_PSR) & mask)
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return AT91_MUX_GPIO;
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select = __raw_readl(pio + PIO_ABSR) & mask;
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return select + 1;
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}
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static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
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{
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return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1;
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}
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static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
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{
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*div = __raw_readl(pio + PIO_SCDR);
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return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1;
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}
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static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
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{
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return (__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1;
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}
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static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
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{
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return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
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}
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static struct at91_pinctrl_mux_ops at91rm9200_ops = {
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.get_periph = at91_mux_get_periph,
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.mux_A_periph = at91_mux_set_A_periph,
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.mux_B_periph = at91_mux_set_B_periph,
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.get_deglitch = at91_mux_get_deglitch,
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.set_deglitch = at91_mux_set_deglitch,
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};
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static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
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.get_periph = at91_mux_pio3_get_periph,
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.mux_A_periph = at91_mux_pio3_set_A_periph,
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.mux_B_periph = at91_mux_pio3_set_B_periph,
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.mux_C_periph = at91_mux_pio3_set_C_periph,
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.mux_D_periph = at91_mux_pio3_set_D_periph,
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.get_deglitch = at91_mux_get_deglitch,
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.set_deglitch = at91_mux_pio3_set_deglitch,
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.get_debounce = at91_mux_pio3_get_debounce,
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.set_debounce = at91_mux_pio3_set_debounce,
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.get_pulldown = at91_mux_pio3_get_pulldown,
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.set_pulldown = at91_mux_pio3_set_pulldown,
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.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
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.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
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};
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static struct of_device_id at91_pinctrl_dt_ids[] = {
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{
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.compatible = "atmel,at91rm9200-pinctrl",
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.data = (unsigned long)&at91rm9200_ops,
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}, {
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.compatible = "atmel,at91sam9x5-pinctrl",
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.data = (unsigned long)&at91sam9x5_ops,
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}, {
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/* sentinel */
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}
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};
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static struct at91_pinctrl_mux_ops *at91_pinctrl_get_driver_data(struct device_d *dev)
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{
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struct at91_pinctrl_mux_ops *ops_data = NULL;
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int rc;
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if (dev->device_node) {
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const struct of_device_id *match;
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match = of_match_node(at91_pinctrl_dt_ids, dev->device_node);
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if (!match)
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ops_data = NULL;
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else
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ops_data = (struct at91_pinctrl_mux_ops *)match->data;
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} else {
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rc = dev_get_drvdata(dev, (unsigned long *)&ops_data);
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if (rc)
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ops_data = NULL;
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}
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return ops_data;
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}
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static int at91_pinctrl_set_conf(struct at91_pinctrl *info, unsigned int pin_num, unsigned int mux, unsigned int conf)
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{
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unsigned int mask;
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void __iomem *pio;
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pio = pin_to_controller(pin_num);
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mask = pin_to_mask(pin_num);
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if (conf & PULL_UP && conf & PULL_DOWN)
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return -EINVAL;
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at91_mux_set_pullup(pio, mask, conf & PULL_UP);
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at91_mux_set_multidrive(pio, mask, conf & MULTI_DRIVE);
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if (info->ops->set_deglitch)
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info->ops->set_deglitch(pio, mask, conf & DEGLITCH);
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if (info->ops->set_debounce)
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info->ops->set_debounce(pio, mask, conf & DEBOUNCE,
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(conf & DEBOUNCE_VAL) >> DEBOUNCE_VAL_SHIFT);
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if (info->ops->set_pulldown)
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info->ops->set_pulldown(pio, mask, conf & PULL_DOWN);
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if (info->ops->disable_schmitt_trig && conf & DIS_SCHMIT)
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info->ops->disable_schmitt_trig(pio, mask);
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return 0;
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}
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static int at91_pinctrl_set_state(struct pinctrl_device *pdev, struct device_node *np)
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{
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struct at91_pinctrl *info;
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const __be32 *list;
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int i, size;
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int ret = 0;
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int bank_num, pin_num, mux, conf;
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info = to_at91_pinctrl(pdev);
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list = of_get_property(np, "atmel,pins", &size);
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size /= sizeof(*list);
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if (!size || size % 4) {
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dev_err(pdev->dev, "wrong pins number or pins and configs should be by 4\n");
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return -EINVAL;
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}
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for (i = 0; i < size; i += 4) {
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bank_num = be32_to_cpu(*list++);
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pin_num = be32_to_cpu(*list++);
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mux = be32_to_cpu(*list++);
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conf = be32_to_cpu(*list++);
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ret = at91_mux_pin(pin_num, mux, conf & PULL_UP);
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if (ret) {
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dev_err(pdev->dev, "failed to mux pin %d\n", pin_num);
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return ret;
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}
|
|
|
|
ret = at91_pinctrl_set_conf(info, pin_num, mux, conf);
|
|
if (ret) {
|
|
dev_err(pdev->dev, "failed to set conf on pin %d\n", pin_num);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct pinctrl_ops at91_pinctrl_ops = {
|
|
.set_state = at91_pinctrl_set_state,
|
|
};
|
|
|
|
static int at91_pinctrl_probe(struct device_d *dev)
|
|
{
|
|
struct at91_pinctrl *info;
|
|
int ret;
|
|
|
|
if (!IS_ENABLED(CONFIG_PINCTRL))
|
|
return 0;
|
|
|
|
info = xzalloc(sizeof(struct at91_pinctrl));
|
|
|
|
info->ops = at91_pinctrl_get_driver_data(dev);
|
|
if (!info->ops) {
|
|
dev_err(dev, "failed to retrieve driver data\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
info->pctl.dev = dev;
|
|
info->pctl.ops = &at91_pinctrl_ops;
|
|
|
|
ret = pinctrl_register(&info->pctl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_info(dev, "AT91 pinctrl registered\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_device_id at91_pinctrl_ids[] = {
|
|
{
|
|
.name = "at91rm9200-pinctrl",
|
|
.driver_data = (unsigned long)&at91rm9200_ops,
|
|
}, {
|
|
.name = "at91sam9x5-pinctrl",
|
|
.driver_data = (unsigned long)&at91sam9x5_ops,
|
|
}, {
|
|
/* sentinel */
|
|
},
|
|
};
|
|
|
|
static struct driver_d at91_pinctrl_driver = {
|
|
.name = "pinctrl-at91",
|
|
.probe = at91_pinctrl_probe,
|
|
.id_table = at91_pinctrl_ids,
|
|
.of_compatible = DRV_OF_COMPAT(at91_pinctrl_dt_ids),
|
|
};
|
|
|
|
static int at91_pinctrl_init(void)
|
|
{
|
|
return platform_driver_register(&at91_pinctrl_driver);
|
|
}
|
|
coredevice_initcall(at91_pinctrl_init);
|
|
|
|
static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
return at91_mux_gpio_get(pio, mask);
|
|
}
|
|
|
|
static void at91_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
at91_mux_gpio_set(pio, mask, value);
|
|
}
|
|
|
|
static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
|
int value)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
at91_mux_gpio_set(pio, mask, value);
|
|
__raw_writel(mask, pio + PIO_OER);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int at91_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
__raw_writel(mask, pio + PIO_ODR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int at91_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
|
|
void __iomem *pio = at91_gpio->regbase;
|
|
unsigned mask = 1 << offset;
|
|
|
|
dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
|
|
'A' + pin_to_bank(chip->base), offset, chip->base + offset);
|
|
at91_mux_gpio_enable(pio, mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void at91_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
dev_dbg(chip->dev, "%s:%d pio%c%d(%d)\n", __func__, __LINE__,
|
|
'A' + pin_to_bank(chip->base), offset, chip->base + offset);
|
|
}
|
|
|
|
static struct gpio_ops at91_gpio_ops = {
|
|
.request = at91_gpio_request,
|
|
.free = at91_gpio_free,
|
|
.direction_input = at91_gpio_direction_input,
|
|
.direction_output = at91_gpio_direction_output,
|
|
.get = at91_gpio_get,
|
|
.set = at91_gpio_set,
|
|
};
|
|
|
|
static struct of_device_id at91_gpio_dt_ids[] = {
|
|
{
|
|
.compatible = "atmel,at91rm9200-gpio",
|
|
.data = (unsigned long)&at91rm9200_ops,
|
|
}, {
|
|
.compatible = "atmel,at91sam9x5-gpio",
|
|
.data = (unsigned long)&at91sam9x5_ops,
|
|
}, {
|
|
/* sentinel */
|
|
},
|
|
};
|
|
|
|
static int at91_gpio_probe(struct device_d *dev)
|
|
{
|
|
struct at91_gpio_chip *at91_gpio;
|
|
struct clk *clk;
|
|
int ret;
|
|
int alias_idx;
|
|
|
|
if (dev->device_node)
|
|
alias_idx = of_alias_get_id(dev->device_node, "gpio");
|
|
else
|
|
alias_idx = dev->id;
|
|
|
|
BUG_ON(alias_idx > MAX_GPIO_BANKS);
|
|
|
|
at91_gpio = &gpio_chip[alias_idx];
|
|
|
|
ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops);
|
|
if (ret) {
|
|
dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
clk = clk_get(dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
dev_err(dev, "clock not found: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_enable(clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "clock failed to enable: %d\n", ret);
|
|
clk_put(clk);
|
|
return ret;
|
|
}
|
|
|
|
gpio_banks = max(gpio_banks, alias_idx + 1);
|
|
at91_gpio->regbase = dev_request_mem_region_err_null(dev, 0);
|
|
if (!at91_gpio->regbase)
|
|
return -ENOENT;
|
|
|
|
at91_gpio->chip.ops = &at91_gpio_ops;
|
|
at91_gpio->chip.ngpio = MAX_NB_GPIO_PER_BANK;
|
|
at91_gpio->chip.dev = dev;
|
|
at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
|
|
|
|
ret = gpiochip_add(&at91_gpio->chip);
|
|
if (ret) {
|
|
dev_err(dev, "couldn't add gpiochip, ret = %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dev_info(dev, "AT91 gpio driver registered\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_device_id at91_gpio_ids[] = {
|
|
{
|
|
.name = "at91rm9200-gpio",
|
|
.driver_data = (unsigned long)&at91rm9200_ops,
|
|
}, {
|
|
.name = "at91sam9x5-gpio",
|
|
.driver_data = (unsigned long)&at91sam9x5_ops,
|
|
}, {
|
|
/* sentinel */
|
|
},
|
|
};
|
|
|
|
static struct driver_d at91_gpio_driver = {
|
|
.name = "gpio-at91",
|
|
.probe = at91_gpio_probe,
|
|
.id_table = at91_gpio_ids,
|
|
.of_compatible = DRV_OF_COMPAT(at91_gpio_dt_ids),
|
|
};
|
|
|
|
static int at91_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&at91_gpio_driver);
|
|
}
|
|
coredevice_initcall(at91_gpio_init);
|