6fe9ee8eb4
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. Even though I should have created an mach-or1200 directory, it is not necessary for now. The OpenRISC 1200 CPU is the only one available and it will be for some time. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
22 lines
377 B
Makefile
22 lines
377 B
Makefile
CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div
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board-$(CONFIG_GENERIC) := generic
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KALLSYMS += --symbol-prefix=_
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archprepare: maketools
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PHONY += maketools
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ifneq ($(board-y),)
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BOARD := arch/openrisc/boards/$(board-y)/
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else
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BOARD :=
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endif
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common-y += $(BOARD)
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common-y += arch/openrisc/lib/
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common-y += arch/openrisc/cpu/
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lds-y += arch/openrisc/cpu/barebox.lds
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