6fe9ee8eb4
OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. Even though I should have created an mach-or1200 directory, it is not necessary for now. The OpenRISC 1200 CPU is the only one available and it will be for some time. Signed-off-by: Franck Jullien <franck.jullien@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
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bitops | ||
barebox.h | ||
bitops.h | ||
byteorder.h | ||
cache.h | ||
common.h | ||
elf.h | ||
io.h | ||
openrisc_exc.h | ||
posix_types.h | ||
ptrace.h | ||
sections.h | ||
spr-defs.h | ||
string.h | ||
swab.h | ||
system.h | ||
types.h |