44 lines
1.4 KiB
C
44 lines
1.4 KiB
C
/*
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* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_OPENRISC_CACHE_H_
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#define __ASM_OPENRISC_CACHE_H_
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void flush_dcache_range(unsigned long addr, unsigned long stop);
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void invalidate_dcache_range(unsigned long addr, unsigned long stop);
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void flush_cache(unsigned long addr, unsigned long size);
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int icache_status(void);
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int checkicache(void);
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int dcache_status(void);
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int checkdcache(void);
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void dcache_enable(void);
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void dcache_disable(void);
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void icache_enable(void);
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void icache_disable(void);
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/*
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* Valid L1 data cache line sizes for the OpenRISC architecture are
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* 16 and 32 bytes.
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* If the board configuration has not specified one we default to the
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* largest of these values for alignment of DMA buffers.
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*/
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
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#else
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#define ARCH_DMA_MINALIGN 32
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#endif
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#endif /* __ASM_OPENRISC_CACHE_H_ */
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