Add basic support for the Xilinx Zynq-7000 EPP architecture. The Zynq-7000 is an embedded processing platform that combines a Cortex A9 dualcore MPSoC with an Artix-7 FPGA. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
57 lines
1.4 KiB
C
57 lines
1.4 KiB
C
/*
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* (c) 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <asm/system.h>
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#include <asm-generic/io.h>
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#include <common.h>
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#include <init.h>
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#include <mach/zynq7000-regs.h>
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static int zynq_init(void)
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{
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u32 val;
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dsb();
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isb();
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writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
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/* remap ocm high */
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writel(0x0000000F, 0xf8000910);
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/* mpcore.filtering_start_address */
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writel(0x00000000, 0xf8f00040);
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/* mpcore.filtering_end_address */
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writel(0xffe00000, 0xf8f00044);
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val = readl(0xf8f00000);
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val |= 0x2;
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writel(val, 0xf8f00000);
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dmb();
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add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL);
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add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
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0x4000, IORESOURCE_MEM, NULL);
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return 0;
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}
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postcore_initcall(zynq_init);
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void __noreturn reset_cpu(unsigned long addr)
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{
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/* write unlock key to slcr */
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writel(0xDF0D, ZYNQ_SLCR_UNLOCK);
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/* reset */
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writel(0x1, ZYNQ_PSS_RST_CTRL);
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while (1)
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;
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}
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