88 lines
3.3 KiB
ArmAsm
88 lines
3.3 KiB
ArmAsm
/**
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* @file
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* @brief Provide Architecture level Initialization
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*
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* This provides OMAP3 Architecture initialization. Among these,
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* @li OMAP ROM Code is located in SRAM, we can piggy back on
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* the same addresses
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* @li If clock initialization is required, call the same.
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* @li Setup a temporary SRAM stack which is necessary to call C
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* functions.
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* @li Call architecture initialization function a_init
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*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/omap3-silicon.h>
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#include <mach/wdt.h>
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#include <mach/clocks.h>
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#include <asm/barebox-arm-head.h>
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.section .text.__omap3_invalidate_dcache
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ENTRY(omap3_invalidate_dcache)
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/* Invalidate all Dcaches */
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#ifndef CONFIG_CPU_V7_DCACHE_SKIP
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/* If Arch specific ROM code SMI handling does not exist */
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mrc p15, 1, r0, c0, c0, 1 /* read clidr */
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ands r3, r0, #0x7000000 /* extract loc from clidr */
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mov r3, r3, lsr #23 /* left align loc bit field */
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beq finished_inval /* if loc is 0, then no need to clean */
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mov r10, #0 /* start clean at cache level 0 */
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inval_loop1:
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add r2, r10, r10, lsr #1 /* work out 3x current cache level */
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mov r1, r0, lsr r2 /* extract cache type bits from clidr */
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and r1, r1, # 7 /* mask of the bits for current cache only */
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cmp r1, #2 /* see what cache we have at this level */
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blt skip_inval /* skip if no cache, or just i-cache */
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mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
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isb /* isb to sych the new cssr&csidr */
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mrc p15, 1, r1, c0, c0, 0 /* read the new csidr */
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and r2, r1, #7 /* extract the length of the cache lines */
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add r2, r2, #4 /* add 4 (line length offset) */
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 /* find maximum number on the way size*/
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clz r5, r4 /* find bit position of way size increment */
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 /* extract max number of the index size */
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inval_loop2:
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mov r9, r4 /* create working copy of max way size */
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inval_loop3:
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ARM( orr r11, r10, r9, lsl r5 ) /* factor way and cache number into r11 */
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ARM( orr r11, r11, r7, lsl r2 ) /* factor index number into r11 */
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THUMB( lsl r6, r9, r5 )
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THUMB( orr r11, r10, r6 ) /* factor way and cache number into r11 */
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THUMB( lsl r6, r7, r2 )
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THUMB( orr r11, r11, r6 ) /* factor index number into r11 */
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mcr p15, 0, r11, c7, c6, 2 /* invalidate by set/way */
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subs r9, r9, #1 /* decrement the way */
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bge inval_loop3
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subs r7, r7, #1 /* decrement the index */
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bge inval_loop2
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skip_inval:
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add r10, r10, #2 /* increment cache number */
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cmp r3, r10
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bgt inval_loop1
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finished_inval:
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mov r10, #0 /* swith back to cache level 0 */
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mcr p15, 2, r10, c0, c0, 0 /* select current cache level in cssr */
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isb
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#endif /* CONFIG_CPU_V7_DCACHE_SKIP */
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/* back to arch calling code */
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bx lr
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ENDPROC(omap3_invalidate_dcache)
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