9
0
Fork 0
barebox/arch
Sascha Hauer 1c9c937a6a ppc mpc5200b: cleanup lowlevel startup
The old startup process consisted of several CFG_LOWBOOT,
CFG_RAMBOOT ifdeffery which I do not understand. So remove
all this and replace it with:

- put the entry point for second stage loaders to offset 0x0
  so that we can do a go /dev/ram0 to start a second barebox
- When we come from the reset vector assume MBAR is at 0x80000000
- When we come from the second stage entry assume that
  SPR 311 is in sync with the current MBAR address.
- Switch MBAR to 0xf0000000 and we are done.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-27 10:27:32 +02:00
..
arm remove EARLY_INIT and EARLY_CONSOLE support 2011-09-27 10:27:18 +02:00
blackfin rename include/mem_malloc.h to include/memory.h 2011-09-23 16:32:48 +02:00
mips remove EARLY_INIT and EARLY_CONSOLE support 2011-09-27 10:27:18 +02:00
nios2 rename include/mem_malloc.h to include/memory.h 2011-09-23 16:32:48 +02:00
ppc ppc mpc5200b: cleanup lowlevel startup 2011-09-27 10:27:32 +02:00
sandbox sandbox: make asm/io.h nonempty 2011-09-23 16:41:17 +02:00
x86 rename include/mem_malloc.h to include/memory.h 2011-09-23 16:32:48 +02:00
architecture.dox MIPS: add documentation 2011-08-05 18:20:17 +02:00