316 lines
8.7 KiB
C
316 lines
8.7 KiB
C
/*
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* (C) Copyright 2010 Juergen Beisert - Pengutronix
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*
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* This code is based partially on code of:
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*
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* (c) 2008 Embedded Alley Solutions, Inc.
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* (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <mach/imx-regs.h>
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#include <mach/generic.h>
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#include <mach/clock.h>
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#define HW_CLKCTRL_PLLCTRL0 0x000
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#define HW_CLKCTRL_PLLCTRL1 0x010
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#define HW_CLKCTRL_CPU 0x20
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# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff)
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# define GET_CPU_PLL_DIV(x) ((x) & 0x3f)
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#define HW_CLKCTRL_HBUS 0x30
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#define HW_CLKCTRL_XBUS 0x40
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#define HW_CLKCTRL_XTAL 0x050
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#define HW_CLKCTRL_PIX 0x060
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/* note: no set/clear register! */
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#define HW_CLKCTRL_SSP 0x070
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/* note: no set/clear register! */
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# define CLKCTRL_SSP_CLKGATE (1 << 31)
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# define CLKCTRL_SSP_BUSY (1 << 29)
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# define CLKCTRL_SSP_DIV_MASK 0x1ff
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# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
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# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK)
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#define HW_CLKCTRL_GPMI 0x080
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# define CLKCTRL_GPMI_CLKGATE (1 << 31)
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# define CLKCTRL_GPMI_DIV_MASK 0x3ff
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/* note: no set/clear register! */
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#define HW_CLKCTRL_SPDIF 0x090
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/* note: no set/clear register! */
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#define HW_CLKCTRL_EMI 0xa0
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/* note: no set/clear register! */
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# define CLKCTRL_EMI_CLKGATE (1 << 31)
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# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf)
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# define GET_EMI_PLL_DIV(x) ((x) & 0x3f)
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#define HW_CLKCTRL_SAIF 0x0c0
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#define HW_CLKCTRL_TV 0x0d0
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#define HW_CLKCTRL_ETM 0x0e0
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#define HW_CLKCTRL_FRAC 0xf0
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# define CLKCTRL_FRAC_CLKGATEIO (1 << 31)
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# define GET_IOFRAC(x) (((x) >> 24) & 0x3f)
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# define SET_IOFRAC(x) (((x) & 0x3f) << 24)
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# define CLKCTRL_FRAC_CLKGATEPIX (1 << 23)
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# define GET_PIXFRAC(x) (((x) >> 16) & 0x3f)
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# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15)
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# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f)
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# define CLKCTRL_FRAC_CLKGATECPU (1 << 7)
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# define GET_CPUFRAC(x) ((x) & 0x3f)
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#define HW_CLKCTRL_FRAC1 0x100
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#define HW_CLKCTRL_CLKSEQ 0x110
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# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
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# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
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# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
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# define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5)
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# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
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#define HW_CLKCTRL_RESET 0x120
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#define HW_CLKCTRL_STATUS 0x130
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#define HW_CLKCTRL_VERSION 0x140
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unsigned imx_get_mpllclk(void)
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{
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/* the main PLL runs at 480 MHz */
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return 480000000;
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}
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unsigned imx_get_xtalclk(void)
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{
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/* the external reference runs at 24 MHz */
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return 24000000;
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}
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/* used for the SDRAM controller */
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unsigned imx_get_emiclk(void)
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{
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uint32_t reg;
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unsigned rate;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE)
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return 0U; /* clock is off */
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI)
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return imx_get_xtalclk() / GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI));
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rate = imx_get_mpllclk() / 1000;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC);
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if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) {
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rate *= 18U;
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rate /= GET_EMIFRAC(reg);
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}
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return (rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)))
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* 1000;
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}
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/*
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* Source of ssp, gpmi, ir
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*/
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unsigned imx_get_ioclk(void)
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{
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uint32_t reg;
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unsigned rate = imx_get_mpllclk() / 1000;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC);
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if (reg & CLKCTRL_FRAC_CLKGATEIO)
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return 0U; /* clock is off */
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rate *= 18U;
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rate /= GET_IOFRAC(reg);
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return rate * 1000;
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}
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/**
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* Setup a new frequency to the IOCLK domain.
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* @param nc New frequency in [Hz]
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*
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* The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35)
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*/
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unsigned imx_set_ioclk(unsigned nc)
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{
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uint32_t reg;
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unsigned div;
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nc /= 1000;
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div = (imx_get_mpllclk() / 1000) * 18;
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div = DIV_ROUND_CLOSEST(div, nc);
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if (div > 0x3f)
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div = 0x3f;
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/* mask the current settings */
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC) & ~(SET_IOFRAC(0x3f));
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writel(reg | SET_IOFRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC);
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/* enable the IO clock at its new frequency */
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writel(CLKCTRL_FRAC_CLKGATEIO, IMX_CCM_BASE + HW_CLKCTRL_FRAC + 8);
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return imx_get_ioclk();
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}
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/* this is CPU core clock */
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unsigned imx_get_armclk(void)
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{
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uint32_t reg;
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unsigned rate;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU)
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return imx_get_xtalclk() / GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU));
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC);
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if (reg & CLKCTRL_FRAC_CLKGATECPU)
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return 0U; /* should not possible, shouldn't it? */
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rate = imx_get_mpllclk() / 1000;
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rate *= 18U;
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rate /= GET_CPUFRAC(reg);
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return (rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)))
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* 1000;
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}
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/* this is the AHB and APBH bus clock */
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unsigned imx_get_hclk(void)
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{
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unsigned rate = imx_get_armclk() / 1000;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) {
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rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f;
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rate = DIV_ROUND_UP(rate, 32);
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} else
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rate = DIV_ROUND_UP(rate,
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readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f);
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return rate * 1000;
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}
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unsigned imx_set_hclk(unsigned nc)
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{
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unsigned root_rate = imx_get_armclk();
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unsigned reg, div;
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div = DIV_ROUND_UP(root_rate, nc);
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if ((div == 0) || (div >= 32))
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return 0;
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if ((root_rate < nc) && (root_rate == 64000000))
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div = 3;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & ~0x3f;
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writel(reg | div, IMX_CCM_BASE + HW_CLKCTRL_HBUS);
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while (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & (1 << 31))
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;
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return imx_get_hclk();
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}
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/*
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* Source of UART, debug UART, audio, PWM, dri, timer, digctl
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*/
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unsigned imx_get_xclk(void)
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{
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unsigned rate = imx_get_xtalclk(); /* runs from the 24 MHz crystal reference */
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return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff);
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}
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/* 'index' gets ignored on i.MX23 */
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unsigned imx_get_sspclk(unsigned index)
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{
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unsigned rate;
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE)
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return 0U; /* clock is off */
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if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_SSP)
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rate = imx_get_xtalclk();
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else
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rate = imx_get_ioclk();
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return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_SSP));
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}
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/**
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* @param index Unit index (ignored on i.MX23)
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* @param nc New frequency in [Hz]
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* @param high != 0 if ioclk should be the source
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* @return The new possible frequency in [kHz]
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*/
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unsigned imx_set_sspclk(unsigned index, unsigned nc, int high)
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{
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uint32_t reg;
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unsigned ssp_div;
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_CLKGATE;
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/* Datasheet says: Do not change the DIV setting if the clock is off */
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writel(reg, IMX_CCM_BASE + HW_CLKCTRL_SSP);
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/* Wait while clock is gated */
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while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE)
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;
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if (high)
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ssp_div = imx_get_ioclk();
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else
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ssp_div = imx_get_xtalclk();
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if (nc > ssp_div) {
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printf("Cannot setup SSP unit clock to %u Hz, base clock is only %u Hz\n", nc, ssp_div);
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ssp_div = 1U;
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} else {
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ssp_div = DIV_ROUND_UP(ssp_div, nc);
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if (ssp_div > CLKCTRL_SSP_DIV_MASK)
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ssp_div = CLKCTRL_SSP_DIV_MASK;
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}
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/* Set new divider value */
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_DIV_MASK;
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writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + HW_CLKCTRL_SSP);
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/* Wait until new divider value is set */
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while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_BUSY)
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;
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if (high)
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/* switch to ioclock */
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writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8);
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else
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/* switch to 24 MHz crystal */
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writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 4);
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return imx_get_sspclk(index);
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}
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void imx_enable_nandclk(void)
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{
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uint32_t reg;
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/* Clear bypass bit; refman says clear, but fsl-code does set. Hooray! */
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writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
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IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET);
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reg = readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI) & ~CLKCTRL_GPMI_CLKGATE;
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writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI);
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udelay(1000);
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/* Initialize DIV to 1 */
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reg &= ~CLKCTRL_GPMI_DIV_MASK;
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reg |= 1;
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writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI);
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}
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void imx_dump_clocks(void)
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{
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printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000);
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printf("arm: %10u kHz\n", imx_get_armclk() / 1000);
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printf("ioclk: %10u kHz\n", imx_get_ioclk() / 1000);
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printf("emiclk: %10u kHz\n", imx_get_emiclk() / 1000);
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printf("hclk: %10u kHz\n", imx_get_hclk() / 1000);
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printf("xclk: %10u kHz\n", imx_get_xclk() / 1000);
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printf("ssp: %10u kHz\n", imx_get_sspclk(0) / 1000);
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}
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