370 lines
8.4 KiB
C
370 lines
8.4 KiB
C
#define pr_fmt(fmt) "cm-fx6: " fmt
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#include <common.h>
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#include <linux/sizes.h>
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#include <mach/generic.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <debug_ll.h>
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#include <io.h>
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#include <mach/imx6-mmdc.h>
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#include <mach/imx6-ddr-regs.h>
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#include <mach/imx6.h>
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#include <mach/xload.h>
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#include <mach/esdctl.h>
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#include <serial/imx-uart.h>
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enum ddr_config {
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DDR_16BIT_256MB,
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DDR_32BIT_512MB,
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DDR_32BIT_1GB,
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DDR_64BIT_1GB,
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DDR_64BIT_2GB,
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DDR_64BIT_4GB,
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DDR_UNKNOWN,
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};
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static void __udelay(int us)
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{
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volatile int i;
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for (i = 0; i < us * 4; i++);
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}
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/*
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* Below DRAM_RESET[DDR_SEL] = 0 which is incorrect according to
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* Freescale QRM, but this is exactly the value used by the automatic
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* calibration script and it works also in all our tests, so we leave
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* it as is at this point.
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*/
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#define CM_FX6_DDR_IOMUX_CFG \
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.dram_sdqs0 = 0x00000038, \
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.dram_sdqs1 = 0x00000038, \
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.dram_sdqs2 = 0x00000038, \
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.dram_sdqs3 = 0x00000038, \
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.dram_sdqs4 = 0x00000038, \
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.dram_sdqs5 = 0x00000038, \
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.dram_sdqs6 = 0x00000038, \
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.dram_sdqs7 = 0x00000038, \
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.dram_dqm0 = 0x00000038, \
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.dram_dqm1 = 0x00000038, \
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.dram_dqm2 = 0x00000038, \
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.dram_dqm3 = 0x00000038, \
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.dram_dqm4 = 0x00000038, \
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.dram_dqm5 = 0x00000038, \
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.dram_dqm6 = 0x00000038, \
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.dram_dqm7 = 0x00000038, \
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.dram_cas = 0x00000038, \
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.dram_ras = 0x00000038, \
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.dram_sdclk_0 = 0x00000038, \
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.dram_sdclk_1 = 0x00000038, \
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.dram_sdcke0 = 0x00003000, \
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.dram_sdcke1 = 0x00003000, \
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.dram_reset = 0x00000038, \
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.dram_sdba2 = 0x00000000, \
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.dram_sdodt0 = 0x00000038, \
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.dram_sdodt1 = 0x00000038,
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#define CM_FX6_GPR_IOMUX_CFG \
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.grp_b0ds = 0x00000038, \
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.grp_b1ds = 0x00000038, \
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.grp_b2ds = 0x00000038, \
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.grp_b3ds = 0x00000038, \
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.grp_b4ds = 0x00000038, \
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.grp_b5ds = 0x00000038, \
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.grp_b6ds = 0x00000038, \
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.grp_b7ds = 0x00000038, \
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.grp_addds = 0x00000038, \
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.grp_ddrmode_ctl = 0x00020000, \
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.grp_ddrpke = 0x00000000, \
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.grp_ddrmode = 0x00020000, \
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.grp_ctlds = 0x00000038, \
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.grp_ddr_type = 0x000C0000,
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static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
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static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
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static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
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static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
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static struct mx6_mmdc_calibration cm_fx6_calib_s = {
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.p0_mpwldectrl0 = 0x005B0061,
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.p0_mpwldectrl1 = 0x004F0055,
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.p0_mpdgctrl0 = 0x0314030C,
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.p0_mpdgctrl1 = 0x025C0268,
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.p0_mprddlctl = 0x42464646,
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.p0_mpwrdlctl = 0x36322C34,
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};
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static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
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.cs1_mirror = 1,
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.cs_density = 16,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 1,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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};
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static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
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.mem_speed = 800,
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.density = 4,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1800,
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.trcmin = 5200,
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.trasmin = 3600,
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.SRT = 0,
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};
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static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
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{
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if (reset)
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((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
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switch (dram_config) {
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case DDR_16BIT_256MB:
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cm_fx6_sysinfo_s.dsize = 0;
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cm_fx6_sysinfo_s.ncs = 1;
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break;
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case DDR_32BIT_512MB:
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cm_fx6_sysinfo_s.dsize = 1;
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cm_fx6_sysinfo_s.ncs = 1;
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break;
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case DDR_32BIT_1GB:
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cm_fx6_sysinfo_s.dsize = 1;
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cm_fx6_sysinfo_s.ncs = 2;
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break;
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default:
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pr_err("Tried to setup invalid DDR configuration\n");
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hang();
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}
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mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
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__udelay(100);
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}
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static struct mx6_mmdc_calibration cm_fx6_calib_q = {
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.p0_mpwldectrl0 = 0x00630068,
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.p0_mpwldectrl1 = 0x0068005D,
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.p0_mpdgctrl0 = 0x04140428,
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.p0_mpdgctrl1 = 0x037C037C,
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.p0_mprddlctl = 0x3C30303A,
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.p0_mpwrdlctl = 0x3A344038,
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.p1_mpwldectrl0 = 0x0035004C,
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.p1_mpwldectrl1 = 0x00170026,
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.p1_mpdgctrl0 = 0x0374037C,
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.p1_mpdgctrl1 = 0x0350032C,
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.p1_mprddlctl = 0x30322A3C,
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.p1_mpwrdlctl = 0x48304A3E,
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};
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static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
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.cs_density = 16,
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.cs1_mirror = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 0,
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.ralat = 5,
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.walat = 1,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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};
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static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
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.mem_speed = 1066,
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.density = 4,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1324,
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.trcmin = 59500,
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.trasmin = 9750,
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.SRT = 0,
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};
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static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
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{
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if (reset)
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((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
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cm_fx6_ddr3_cfg_q.rowaddr = 14;
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switch (dram_config) {
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case DDR_16BIT_256MB:
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cm_fx6_sysinfo_q.dsize = 0;
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cm_fx6_sysinfo_q.ncs = 1;
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break;
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case DDR_32BIT_512MB:
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cm_fx6_sysinfo_q.dsize = 1;
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cm_fx6_sysinfo_q.ncs = 1;
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break;
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case DDR_64BIT_1GB:
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cm_fx6_sysinfo_q.dsize = 2;
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cm_fx6_sysinfo_q.ncs = 1;
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break;
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case DDR_64BIT_2GB:
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cm_fx6_sysinfo_q.cs_density = 8;
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cm_fx6_ddr3_cfg_q.density = 2;
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cm_fx6_sysinfo_q.dsize = 2;
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cm_fx6_sysinfo_q.ncs = 2;
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break;
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case DDR_64BIT_4GB:
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cm_fx6_sysinfo_q.dsize = 2;
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cm_fx6_sysinfo_q.ncs = 2;
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cm_fx6_ddr3_cfg_q.rowaddr = 15;
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break;
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default:
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pr_err("Tried to setup invalid DDR configuration\n");
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hang();
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}
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mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
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__udelay(100);
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}
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static unsigned long cm_fx6_spl_dram_init(void)
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{
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unsigned long bank1_size, bank2_size;
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int cpu_type = __imx6_cpu_type();
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if (cpu_type == IMX6_CPUTYPE_IMX6S) {
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mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
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spl_mx6s_dram_init(DDR_32BIT_1GB, false);
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bank1_size = get_ram_size((long int *)0x10000000, 0x80000000);
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bank2_size = get_ram_size((long int *)0x80000000, 0x80000000);
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if (bank1_size == 0x20000000) {
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if (bank2_size == 0x20000000)
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return SZ_1G;
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spl_mx6s_dram_init(DDR_32BIT_512MB, true);
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return SZ_512M;
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}
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spl_mx6s_dram_init(DDR_16BIT_256MB, true);
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bank1_size = get_ram_size((long int *)0x10000000, 0x80000000);
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if (bank1_size == 0x10000000)
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return SZ_256M;
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} else if (cpu_type == IMX6_CPUTYPE_IMX6D || cpu_type == IMX6_CPUTYPE_IMX6Q) {
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mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
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spl_mx6q_dram_init(DDR_64BIT_4GB, false);
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bank1_size = get_ram_size((long int *)0x10000000, 0x80000000);
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if (bank1_size == 0x80000000)
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return SZ_2G;
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if (bank1_size == 0x40000000) {
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bank2_size = get_ram_size((long int *)0x90000000,
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0x40000000);
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if (bank2_size == 0x40000000) {
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/* Don't do a full reset here */
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spl_mx6q_dram_init(DDR_64BIT_2GB, false);
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return SZ_2G;
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} else {
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spl_mx6q_dram_init(DDR_64BIT_1GB, true);
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return SZ_1G;
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}
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}
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spl_mx6q_dram_init(DDR_32BIT_512MB, true);
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bank1_size = get_ram_size((long int *)0x10000000, 0x80000000);
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if (bank1_size == 0x20000000)
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return SZ_512M;
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spl_mx6q_dram_init(DDR_16BIT_256MB, true);
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bank1_size = get_ram_size((long int *)0x10000000, 0x80000000);
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if (bank1_size == 0x10000000)
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return SZ_256M;
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}
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return 0;
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}
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static inline void setup_uart(void)
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{
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void __iomem *iomuxbase = (void *)MX6_IOMUXC_BASE_ADDR;
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writel(0x4, iomuxbase + 0x01f8);
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imx6_ungate_all_peripherals();
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imx6_uart_setup((void *)MX6_UART4_BASE_ADDR);
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pbl_set_putc(imx_uart_putc, (void *)MX6_UART4_BASE_ADDR);
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pr_debug("\n");
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}
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static void cm_fx6_init(void)
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{
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unsigned long sdram_size;
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setup_uart();
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if (get_pc() > 0x10000000)
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return;
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sdram_size = cm_fx6_spl_dram_init();
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pr_debug("SDRAM init finished. SDRAM size 0x%08lx\n", sdram_size);
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imx6_esdhc_start_image(2);
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pr_info("Loading image from SPI flash\n");
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imx6_spi_start_image(0);
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}
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extern char __dtb_imx6q_cm_fx6_start[];
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extern char __dtb_imx6dl_cm_fx6_start[];
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static noinline void cm_fx6_start(void)
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{
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int cpu_type = __imx6_cpu_type();
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cm_fx6_init();
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if (cpu_type == IMX6_CPUTYPE_IMX6S)
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imx6q_barebox_entry(__dtb_imx6dl_cm_fx6_start);
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else
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imx6q_barebox_entry(__dtb_imx6q_cm_fx6_start);
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}
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ENTRY_FUNCTION(start_imx6_cm_fx6, r0, r1, r2)
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{
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arm_cpu_lowlevel_init();
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relocate_to_current_adr();
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setup_c();
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barrier();
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cm_fx6_start();
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}
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extern char __dtb_imx6q_utilite_start[];
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extern char __dtb_imx6dl_utilite_value_start[];
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static noinline void utilite_start(void)
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{
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int cpu_type = __imx6_cpu_type();
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cm_fx6_init();
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if (cpu_type == IMX6_CPUTYPE_IMX6S)
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/* FIXME: This needs a specialized utilite value dts */
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imx6q_barebox_entry(__dtb_imx6dl_cm_fx6_start);
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else
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imx6q_barebox_entry(__dtb_imx6q_utilite_start);
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}
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ENTRY_FUNCTION(start_imx6_utilite, r0, r1, r2)
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{
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arm_cpu_lowlevel_init();
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relocate_to_current_adr();
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setup_c();
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barrier();
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utilite_start();
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}
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