193 lines
4.6 KiB
C
193 lines
4.6 KiB
C
#include <common.h>
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#include <init.h>
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#include <io.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <linux/sizes.h>
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#include <mach/pxa-regs.h>
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#include <mach/regs-ost.h>
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/*
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* Memory settings
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*/
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#define DEFAULT_MSC0_VAL 0x23d223d2
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#define DEFAULT_MSC1_VAL 0x3ff1a441
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#define DEFAULT_MSC2_VAL 0x7ff17ff1
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#define DEFAULT_MDCNFG_VAL 0x00001ac9
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#define DEFAULT_MDREFR_VAL 0x00018018
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#define DEFAULT_MDMRS_VAL 0x00000000
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#define DEFAULT_FLYCNFG_VAL 0x00000000
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#define DEFAULT_SXCNFG_VAL 0x00000000
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/*
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* PCMCIA and CF Interfaces
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*/
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#define DEFAULT_MECR_VAL 0x00000000
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#define DEFAULT_MCMEM0_VAL 0x00010504
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#define DEFAULT_MCMEM1_VAL 0x00010504
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#define DEFAULT_MCATT0_VAL 0x00010504
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#define DEFAULT_MCATT1_VAL 0x00010504
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#define DEFAULT_MCIO0_VAL 0x00004715
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#define DEFAULT_MCIO1_VAL 0x00004715
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static inline void writelrb(uint32_t val, volatile u32 __iomem *addr)
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{
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writel(val, addr);
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barrier();
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readl(addr);
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barrier();
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}
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static inline void pxa_wait_ticks(int ticks)
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{
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writel(0, &OSCR);
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while (readl(&OSCR) < ticks)
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barrier();
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}
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static inline void pxa2xx_dram_init(void)
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{
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uint32_t tmp;
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int i;
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/*
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* 1) Initialize Asynchronous static memory controller
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*/
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writelrb(DEFAULT_MSC0_VAL, &MSC0);
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writelrb(DEFAULT_MSC1_VAL, &MSC1);
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writelrb(DEFAULT_MSC2_VAL, &MSC2);
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/*
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* 2) Initialize Card Interface
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*/
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/* MECR: Memory Expansion Card Register */
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writelrb(DEFAULT_MECR_VAL, &MECR);
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/* MCMEM0: Card Interface slot 0 timing */
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writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0);
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/* MCMEM1: Card Interface slot 1 timing */
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writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1);
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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writelrb(DEFAULT_MCATT0_VAL, &MCATT0);
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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writelrb(DEFAULT_MCATT1_VAL, &MCATT1);
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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writelrb(DEFAULT_MCIO0_VAL, &MCIO0);
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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writelrb(DEFAULT_MCIO1_VAL, &MCIO1);
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/*
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* 3) Configure Fly-By DMA register
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*/
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writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG);
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/*
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* 4) Initialize Timing for Sync Memory (SDCLK0)
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*/
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/*
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* Before accessing MDREFR we need a valid DRI field, so we set
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* this to power on defaults + DRI field.
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*/
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/* Read current MDREFR config and zero out DRI */
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tmp = readl(&MDREFR) & ~0xfff;
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/* Add user-specified DRI */
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tmp |= DEFAULT_MDREFR_VAL & 0xfff;
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/* Configure important bits */
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tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
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tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
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/* Write MDREFR back */
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writelrb(tmp, &MDREFR);
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/*
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* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
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*/
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/* Initialize SXCNFG register. Assert the enable bits.
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*
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* Write SXMRS to cause an MRS command to all enabled banks of
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* synchronous static memory. Note that SXLCR need not be written
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* at this time.
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*/
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writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG);
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/*
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* 6) Initialize SDRAM
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*/
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writelrb(DEFAULT_MDREFR_VAL & ~MDREFR_SLFRSH, &MDREFR);
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writelrb(DEFAULT_MDREFR_VAL | MDREFR_E1PIN, &MDREFR);
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/*
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* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
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* but not enable each SDRAM partition pair.
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*/
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writelrb(DEFAULT_MDCNFG_VAL &
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~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), &MDCNFG);
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/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
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pxa_wait_ticks(0x300);
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/*
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* 8) Trigger a number (usually 8) refresh cycles by attempting
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* non-burst read or write accesses to disabled SDRAM, as commonly
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* specified in the power up sequence documented in SDRAM data
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* sheets. The address(es) used for this purpose must not be
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* cacheable.
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*/
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for (i = 9; i >= 0; i--) {
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writel(i, 0xa0000000);
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barrier();
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}
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/*
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* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
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*/
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tmp = DEFAULT_MDCNFG_VAL &
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(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
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tmp |= readl(&MDCNFG);
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writelrb(tmp, &MDCNFG);
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/*
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* 10) Write MDMRS.
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*/
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writelrb(DEFAULT_MDMRS_VAL, &MDMRS);
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/*
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* 11) Enable APD
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*/
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if (DEFAULT_MDREFR_VAL & MDREFR_APD) {
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tmp = readl(&MDREFR);
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tmp |= MDREFR_APD;
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writelrb(tmp, &MDREFR);
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}
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}
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void __bare_init __naked barebox_arm_reset_vector(void)
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{
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unsigned long pssr = PSPR;
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unsigned long pc = get_pc();
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arm_cpu_lowlevel_init();
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CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART;
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/*
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* When not running from SDRAM, get it out of self refresh, and/or
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* initialize it.
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*/
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if (!(pc >= 0xa0000000 && pc < 0xb0000000))
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pxa2xx_dram_init();
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if ((pssr >= 0xa0000000 && pssr < 0xb0000000) ||
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(pssr >= 0x04000000 && pssr < 0x10000000))
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asm("mov pc, %0" : : "r"(pssr) : );
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barebox_arm_entry(0xa0000000, SZ_64M, 0);
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}
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