373 lines
9.7 KiB
C
373 lines
9.7 KiB
C
/*
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* drivers/net/phy/micrel.c
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*
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* Driver for Micrel PHYs
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*
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* Author: David J. Choi
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*
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* Copyright (c) 2010 Micrel, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Support : ksz9021 1000/100/10 phy from Micrel
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* ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy
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*/
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#include <common.h>
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#include <init.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/micrel_phy.h>
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/* Operation Mode Strap Override */
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#define MII_KSZPHY_OMSO 0x16
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#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
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#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
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#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
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/* general PHY control reg in vendor specific block. */
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#define MII_KSZPHY_CTRL 0x1F
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/* bitmap of PHY register to set interrupt mode */
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#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
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#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
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#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
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/* Write/read to/from extended registers */
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#define MII_KSZPHY_EXTREG 0x0b
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#define KSZPHY_EXTREG_WRITE 0x8000
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#define MII_KSZPHY_EXTREG_WRITE 0x0c
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#define MII_KSZPHY_EXTREG_READ 0x0d
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/* Extended registers */
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#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
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#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
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#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
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#define PS_TO_REG 200
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static int kszphy_extended_write(struct phy_device *phydev,
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u32 regnum, u16 val)
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{
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phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
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return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
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}
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static int kszphy_extended_read(struct phy_device *phydev,
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u32 regnum)
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{
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phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
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return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
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}
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static int kszphy_config_init(struct phy_device *phydev)
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{
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return 0;
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}
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static int ksz8021_config_init(struct phy_device *phydev)
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{
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const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
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phy_write(phydev, MII_KSZPHY_OMSO, val);
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return 0;
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}
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static int ks8051_config_init(struct phy_device *phydev)
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{
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int regval;
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if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
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regval = phy_read(phydev, MII_KSZPHY_CTRL);
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regval |= KSZ8051_RMII_50MHZ_CLK;
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phy_write(phydev, MII_KSZPHY_CTRL, regval);
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}
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return 0;
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}
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static int ksz9021_load_values_from_of(struct phy_device *phydev,
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struct device_node *of_node, u16 reg,
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const char *field[])
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{
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int val, regval, i;
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regval = kszphy_extended_read(phydev, reg);
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for (i = 0; i < 4; i++) {
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int shift = i * 4;
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if (of_property_read_u32(of_node, field[i], &val))
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continue;
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regval &= ~(0xf << shift);
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regval |= ((val / PS_TO_REG) & 0xf) << shift;
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}
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return kszphy_extended_write(phydev, reg, regval);
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}
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static int ksz9021_config_init(struct phy_device *phydev)
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{
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struct device_d *dev = &phydev->dev;
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struct device_node *of_node = dev->device_node;
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const char *clk_pad_skew_names[] = {
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"txen-skew-ps", "txc-skew-ps",
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"rxdv-skew-ps", "rxc-skew-ps"
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};
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const char *rx_pad_skew_names[] = {
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"rxd0-skew-ps", "rxd1-skew-ps",
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"rxd2-skew-ps", "rxd3-skew-ps"
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};
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const char *tx_pad_skew_names[] = {
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"txd0-skew-ps", "txd1-skew-ps",
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"txd2-skew-ps", "txd3-skew-ps"
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};
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if (!of_node && dev->parent->device_node)
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of_node = dev->parent->device_node;
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if (of_node) {
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
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clk_pad_skew_names);
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_RX_DATA_PAD_SKEW,
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rx_pad_skew_names);
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ksz9021_load_values_from_of(phydev, of_node,
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MII_KSZPHY_TX_DATA_PAD_SKEW,
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tx_pad_skew_names);
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}
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return 0;
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}
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#define KSZ9031_PS_TO_REG 60
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/* Extended registers */
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#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
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#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
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#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
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#define MII_KSZ9031RN_CLK_PAD_SKEW 8
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static int ksz9031_of_load_skew_values(struct phy_device *phydev,
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struct device_node *of_node,
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u16 reg, size_t field_sz,
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char *field[], u8 numfields)
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{
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int val[4] = {-1, -2, -3, -4};
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int matches = 0;
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u16 mask;
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u16 maxval;
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u16 newval;
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int i;
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for (i = 0; i < numfields; i++)
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if (!of_property_read_u32(of_node, field[i], val + i))
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matches++;
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if (!matches)
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return 0;
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if (matches < numfields)
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newval = phy_read_mmd_indirect(phydev, reg, 2);
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else
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newval = 0;
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maxval = (field_sz == 4) ? 0xf : 0x1f;
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for (i = 0; i < numfields; i++)
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if (val[i] != -(i + 1)) {
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mask = 0xffff;
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mask ^= maxval << (field_sz * i);
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newval = (newval & mask) |
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(((val[i] / KSZ9031_PS_TO_REG) & maxval)
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<< (field_sz * i));
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}
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phy_write_mmd_indirect(phydev, reg, 2, newval);
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return 0;
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}
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static int ksz9031_config_init(struct phy_device *phydev)
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{
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struct device_d *dev = &phydev->dev;
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struct device_node *of_node = dev->device_node;
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char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
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char *rx_data_skews[4] = {
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"rxd0-skew-ps", "rxd1-skew-ps",
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"rxd2-skew-ps", "rxd3-skew-ps"
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};
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char *tx_data_skews[4] = {
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"txd0-skew-ps", "txd1-skew-ps",
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"txd2-skew-ps", "txd3-skew-ps"
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};
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char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
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if (!of_node && dev->parent->device_node)
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of_node = dev->parent->device_node;
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if (of_node) {
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_CLK_PAD_SKEW, 5,
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clk_skews, 2);
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
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control_skews, 2);
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
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rx_data_skews, 4);
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ksz9031_of_load_skew_values(phydev, of_node,
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MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
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tx_data_skews, 4);
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}
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return 0;
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}
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#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
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#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
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#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
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int ksz8873mll_read_status(struct phy_device *phydev)
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{
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int regval;
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/* dummy read */
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regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
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regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
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if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
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phydev->duplex = DUPLEX_HALF;
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else
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phydev->duplex = DUPLEX_FULL;
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if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
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phydev->speed = SPEED_10;
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else
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phydev->speed = SPEED_100;
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phydev->link = 1;
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phydev->pause = phydev->asym_pause = 0;
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return 0;
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}
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static int ksz8873mll_config_aneg(struct phy_device *phydev)
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{
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return 0;
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}
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static int ksz8873mll_config_init(struct phy_device *phydev)
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{
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phydev->autoneg = AUTONEG_DISABLE;
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phydev->link = 1;
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return 0;
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}
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static struct phy_driver ksphy_driver[] = {
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{
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.phy_id = PHY_ID_KS8737,
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.phy_id_mask = 0x00fffff0,
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.drv.name = "Micrel KS8737",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.config_init = kszphy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8021,
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.phy_id_mask = 0x00ffffff,
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.drv.name = "Micrel KSZ8021",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
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SUPPORTED_Asym_Pause),
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.config_init = ksz8021_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8031,
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.phy_id_mask = 0x00ffffff,
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.drv.name = "Micrel KSZ8031",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
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SUPPORTED_Asym_Pause),
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.config_init = ksz8021_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8041,
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.phy_id_mask = 0x00fffff0,
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.drv.name = "Micrel KSZ8041",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
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| SUPPORTED_Asym_Pause),
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.config_init = kszphy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8051,
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.phy_id_mask = 0x00fffff0,
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.drv.name = "Micrel KSZ8051",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
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| SUPPORTED_Asym_Pause),
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.config_init = ks8051_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8081,
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.phy_id_mask = MICREL_PHY_ID_MASK,
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.drv.name = "Micrel KSZ8081/91",
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.config_init = kszphy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8001,
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.drv.name = "Micrel KSZ8001 or KS8721",
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.phy_id_mask = 0x00ffffff,
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.features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
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.config_init = kszphy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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/*
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* Due to a hw bug do not enable the Asym_Pause.
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* Otherwise if you set the bit 11 in 4h you will have to unplug
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* and replug the cable to make the phy work.
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*/
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.phy_id = PHY_ID_KSZ9021,
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.phy_id_mask = 0x000ffffe,
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.drv.name = "Micrel KSZ9021 Gigabit PHY",
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.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
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.config_init = ksz9021_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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/* I saw the same issue like PHY_ID_KSZ9021 for Asym_Pause */
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.phy_id = PHY_ID_KSZ9031,
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.phy_id_mask = 0x00fffff0,
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.drv.name = "Micrel KSZ9031 Gigabit PHY",
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.features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
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.config_init = ksz9031_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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}, {
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.phy_id = PHY_ID_KSZ8873MLL,
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.phy_id_mask = 0x00fffff0,
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.drv.name = "Micrel KSZ8873MLL Switch",
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.features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
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.config_init = ksz8873mll_config_init,
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.config_aneg = ksz8873mll_config_aneg,
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.read_status = ksz8873mll_read_status,
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} };
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static int ksphy_init(void)
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{
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return phy_drivers_register(ksphy_driver,
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ARRAY_SIZE(ksphy_driver));
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}
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fs_initcall(ksphy_init);
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