261 lines
7.7 KiB
C
261 lines
7.7 KiB
C
#include <common.h>
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#include <io.h>
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#include <init.h>
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#include <sizes.h>
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#include <asm/barebox-arm-head.h>
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#include <asm/barebox-arm.h>
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#include <mach/omap3-mux.h>
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#include <mach/sdrc.h>
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#include <mach/control.h>
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#include <mach/syslib.h>
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#include <mach/omap3-silicon.h>
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#include <mach/sys_info.h>
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/* Slower full frequency range default timings for x32 operation */
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#define SDP_SDRC_SHARING 0x00000100
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/* Diabling power down mode using CKE pin */
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#define SDP_SDRC_POWER_POP 0x00000081
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/* rkw - need to find of 90/72 degree recommendation for speed like before. */
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#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
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(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
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/* used to create an array of memory configuartions. */
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struct sdrc_config {
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u32 cs_cfg;
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u32 mcfg;
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u32 mr;
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u32 actim_ctrla;
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u32 actim_ctrlb;
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u32 rfr_ctrl;
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} const sdrc_config[] = {
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/* max cs_size for autodetection, common timing */
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/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
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{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
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/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
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{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
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/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
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{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
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/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
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{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
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};
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/*
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* Boot-time initialization(s)
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*/
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/*********************************************************************
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* init_sdram_ddr() - Init DDR controller.
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*********************************************************************/
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void init_sdram_ddr(void)
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{
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/* reset sdrc controller */
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writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
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wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
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writel(0, OMAP3_SDRC_REG(SYSCONFIG));
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/* setup sdrc to ball mux */
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writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
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writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
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/* set up dll */
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writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
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sdelay(0x2000); /* give time to lock */
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}
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/*********************************************************************
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* config_sdram_ddr() - Init DDR on dev board.
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*********************************************************************/
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void config_sdram_ddr(u8 cs, u8 cfg)
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{
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writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
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writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
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writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
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writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
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writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
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sdelay(5000);
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writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
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writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
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writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
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/* set mr0 */
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writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
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sdelay(2000);
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}
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/**
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* @brief Initialize the SDRC module
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* Initialisation for 1x256MByte but normally
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* done by x-loader.
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* @return void
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*/
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static void pcaal1_sdrc_init(void)
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{
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u32 test0, test1;
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char cfg;
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init_sdram_ddr();
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config_sdram_ddr(0, 0); /* 256MByte at CS0 */
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config_sdram_ddr(1, 0); /* 256MByte at CS1 */
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test0 = get_ram_size((long *) 0x80000000, SZ_256M);
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test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
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/* mask out lower nible, its not tested with
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in common/memsize.c */
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test1 &= 0xfffffff0;
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if ((test1 > 0) && (test1 != test0))
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hang();
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cfg = -1; /* illegal configuration found */
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if (test1 == 0) {
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init_sdram_ddr();
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writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
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/* 1 x 256MByte */
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if (test0 == SZ_256M)
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cfg = 2;
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if (cfg != -1) {
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config_sdram_ddr(0, cfg);
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writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
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}
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return;
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}
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/* reinit both cs with correct size */
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/* 2 x 128MByte */
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if (test0 == SZ_128M)
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cfg = 1;
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/* 2 x 256MByte */
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if (test0 == SZ_256M)
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cfg = 3;
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if (cfg != -1) {
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init_sdram_ddr();
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writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
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config_sdram_ddr(0, cfg);
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config_sdram_ddr(1, cfg);
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}
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}
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/**
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* @brief Do the necessary pin muxing required for phyCARD-A-L1.
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* Some pins in OMAP3 do not have alternate modes.
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* We don't program these pins.
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*
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* See @ref MUX_VAL for description of the muxing mode.
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*
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* @return void
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*/
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static void pcaal1_mux_config(void)
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{
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/*
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* Serial Interface
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*/
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
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/* ETH_PME (GPIO_55) */
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MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M4));
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/* #CS5 (Ethernet) */
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MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0));
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/* ETH_FIFO_SEL (GPIO_57) */
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MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M4));
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/* ETH_AMDIX_EN (GPIO_58) */
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MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M4));
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/* ETH_nRST (GPIO_64) */
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MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTU | EN | M4));
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/* HSMMC1 */
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MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
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MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
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/* USBOTG_nRST (GPIO_63) */
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MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4));
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/* USBH_nRST (GPIO_65) */
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MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4));
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}
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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static int pcaal1_board_init(void)
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{
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int in_sdram = running_in_sdram();
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if (!in_sdram)
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omap3_core_init();
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pcaal1_mux_config();
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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pcaal1_sdrc_init();
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return 0;
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}
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void __naked barebox_arm_reset_vector(void)
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{
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arm_cpu_lowlevel_init();
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pcaal1_board_init();
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barebox_arm_entry(0x80000000, SZ_256M, 0);
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}
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