134 lines
3.4 KiB
ArmAsm
134 lines
3.4 KiB
ArmAsm
#include <config.h>
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#include <asm-generic/memory_layout.h>
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#include <mach/imx27-regs.h>
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#include <mach/esdctl.h>
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#include <asm/barebox-arm-head.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
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#define ROWS0 ESDCTL0_ROW14
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#define CFG0 0x0029572D
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#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
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#define ROWS0 ESDCTL0_ROW13
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#define CFG0 0x00095728
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#endif
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#define ESDCTL0_VAL (ESDCTL0_SDE | ROWS0 | ESDCTL0_COL10)
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.macro sdram_init
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/*
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* DDR on CSD0
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*/
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/* Enable DDR SDRAM operation */
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writel(0x0000000C, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
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/* Set the driving strength */
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writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(3))
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writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(5))
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writel(0x55555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(6))
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writel(0x00005005, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(7))
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writel(0x15555555, MX27_SYSCTRL_BASE_ADDR + MX27_DSCR(8))
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/* Initial reset */
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writel(0x00000004, MX27_ESDCTL_BASE_ADDR + IMX_ESDMISC)
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writel(CFG0, MX27_ESDCTL_BASE_ADDR + IMX_ESDCFG0)
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/* precharge CSD0 all banks */
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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writel(0x00000000, 0xA0000F00) /* CSD0 precharge address (A10 = 1) */
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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ldr r0, =0xa0000f00
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mov r1, #0
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mov r2, #8
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1:
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str r1, [r0]
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subs r2, #1
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bne 1b
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writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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#if defined CONFIG_EUKREA_CPUIMX27_SDRAM_256MB
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ldr r0, =0xA2000000
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#elif defined CONFIG_EUKREA_CPUIMX27_SDRAM_128MB
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ldr r0, =0xA1000000
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#endif
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mov r1, #0xff
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strb r1, [r0]
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writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
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ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
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MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0)
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.endm
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.section ".text_bare_init","ax"
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.globl reset
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reset:
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common_reset r0
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/* ahb lite ip interface */
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writel(0x20040304, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR0)
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writel(0xDFFBFCFB, MX27_AIPI_BASE_ADDR + MX27_AIPI1_PSR1)
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writel(0x00000000, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR0)
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writel(0xFFFFFFFF, MX27_AIPI_BASE_ADDR + MX27_AIPI2_PSR1)
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/* disable mpll/spll */
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ldr r0, =MX27_CCM_BASE_ADDR + MX27_CSCR
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ldr r1, [r0]
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bic r1, r1, #0x03
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str r1, [r0]
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*/
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/* MPLL = 399 MHz */
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writel(0x00331C23, MX27_CCM_BASE_ADDR + MX27_MPCTL0)
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/* SPLL = 240 MHz */
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writel(0x040C2403, MX27_CCM_BASE_ADDR + MX27_SPCTL0)
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writel(0x33F38107 | MX27_CSCR_MPLL_RESTART | MX27_CSCR_SPLL_RESTART,
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MX27_CCM_BASE_ADDR + MX27_CSCR)
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/* add some delay here */
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mov r1, #0x1000
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1: subs r1, r1, #0x1
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bne 1b
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/* clock gating enable */
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writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR)
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/* peripheral clock divider */
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/* FIXME */
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writel(0x130400c3, MX27_CCM_BASE_ADDR + MX27_PCDR0)
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/* PERDIV1=08 @133 MHz */
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writel(0x09030208, MX27_CCM_BASE_ADDR + MX27_PCDR1)
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/* PERDIV1=04 @266 MHz */
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/* skip sdram initialization if we run from ram */
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cmp pc, #0xa0000000
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bls 1f
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cmp pc, #0xc0000000
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bhi 1f
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b board_init_lowlevel_return
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1:
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sdram_init
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
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b imx27_barebox_boot_nand_external
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#endif /* CONFIG_NAND_IMX_BOOT */
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ret:
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b board_init_lowlevel_return
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